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54 lines
1.2 KiB
Verilog
54 lines
1.2 KiB
Verilog
// # falling edge FF (output in_sh) follwowed by rising edge FF
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// # has the following schematic representation:
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// #
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// # negedge FF -> posedge FF
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// # || ||
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// # \/ \/
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// # lat1-lat0 -> lat0-lat1
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// # ||
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// # \/
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// # lat1-lat0 -> lat1
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// # || ||
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// # \/ \/
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// # negedge FF -> lat1
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module oh_lat1 (/*AUTOARG*/
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// Outputs
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out_sl,
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// Inputs
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in_sh, clk
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);
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parameter DW=99;
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input [DW-1:0] in_sh;
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input clk;
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output [DW-1:0] out_sl;
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// # lat_clk is created in the following way:
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// # 1. clk_en -> lat0 -> clk_en_sh
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// # 2. lat_clk = clk_en_sh & clk
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reg [DW-1:0] out_real_sl;
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wire [DW-1:0] out_sl;
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/* verilator lint_off COMBDLY */
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// # Real lat1
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always @ (clk or in_sh)
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if (clk)
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out_real_sl[DW-1:0] <= in_sh[DW-1:0];
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/* verilator lint_on COMBDLY */
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`ifdef DV_FAKELAT
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// # posedge FF
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reg [DW-1:0] out_dv_sl;
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always @ (posedge clk)
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out_dv_sl[DW-1:0] <= in_sh[DW-1:0];
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assign out_sl[DW-1:0] = out_dv_sl[DW-1:0];
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`else
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assign out_sl[DW-1:0] = out_real_sl[DW-1:0];
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`endif // !`ifdef CFG_FAKELAT
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endmodule // lat1
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