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94 lines
2.6 KiB
Verilog
94 lines
2.6 KiB
Verilog
module oh_memory_sp(/*AUTOARG*/
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// Outputs
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dout,
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// Inputs
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clk, en, we, wem, addr, din, vdd, vddm, sleep, shutdown, repair,
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bist_en, bist_we, bist_wem, bist_addr, bist_din
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);
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// parameters
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parameter DW = 32; // memory width
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parameter DEPTH = 14; // memory depth
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parameter RW = 32; // repair vector width
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parameter PROJ = ""; // project name (used for IP selection)
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localparam AW = $clog2(DEPTH); // address bus width
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// standard memory interface
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input clk; // clock
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input en; // memory access
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input we; // write enable global signal
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input [DW-1:0] wem; // write enable vector
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input [AW-1:0] addr; // address
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input [DW-1:0] din; // data input
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output [DW-1:0] dout; // data output
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// Power/repai interface (ASICs only)
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input vdd; // periphery power rail
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input vddm; // array power rail
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input sleep; // sleep (content retained)
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input shutdown; // shutdown (no retention)
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input [RW-1:0] repair; // "wildcard" repair vector
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// BIST interface (ASICs only)
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input bist_en; // bist enable
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input bist_we; // write enable global signal
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input [DW-1:0] bist_wem; // write enable vector
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input [AW-1:0] bist_addr; // address
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input [DW-1:0] bist_din; // data input
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`ifdef CFG_ASIC
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//Actual IP hidden behind wrapper to protect the innocent
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sram_sp #(.DW(DW).
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.DEPTH(DEPTH),
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.PROJ(PROJ),
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.RW(RW))
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sram_sp (// Outputs
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.dout (dout[DW-1:0]),
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// Inputs
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.clk (clk),
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.en (en),
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.we (we),
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.wem (wem[DW-1:0]),
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.addr (addr[AW-1:0]),
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.din (din[DW-1:0]),
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.vdd (vdd),
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.vddm (vddm),
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.sleep (sleep),
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.shutdown (shutdown),
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.cfg_repair (cfg_repair[RW-1:0]),
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.bist_en (bist_en),
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.bist_we (bist_we),
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.bist_wem (bist_wem[DW-1:0]),
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.bist_addr (bist_addr[AW-1:0]),
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.bist_din (bist_din[DW-1:0]));
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`else
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//Assume FPGA tool knows what it's doing (single clock...)
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reg [DW-1:0] ram [DEPTH-1:0];
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reg [DW-1:0] dout;
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integer i;
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//read port (one cycle latency)
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always @ (posedge clk)
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if(en)
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dout[DW-1:0] <= ram[addr[AW-1:0]];
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//write port
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always @ (posedge clk)
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for(i=0;i<DW;i=i+1)
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if(en & wem[i] & we)
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ram[addr[AW-1:0]][i] <= din[i];
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`endif
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endmodule // oh_memory_sp
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