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117 lines
4.7 KiB
Verilog
117 lines
4.7 KiB
Verilog
//#############################################################################
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//# Purpose: Parallel to Serial Converter #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see below) #
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//#############################################################################
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module oh_par2ser (/*AUTOARG*/
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// Outputs
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dout, access_out, wait_out,
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// Inputs
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clk, nreset, din, load, shift, datasize, lsbfirst, fill, wait_in
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);
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//###########################
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//# INTERFACE
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//###########################
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// parameters
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parameter PW = 64; // parallel packet width
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parameter SW = 1; // serial packet width
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localparam CW = $clog2(PW/SW); // serialization factor (for counter)
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// reset, clk
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input clk; // sampling clock
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input nreset; // async active low reset
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// data interface
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input [PW-1:0] din; // parallel data
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output [SW-1:0] dout; // serial output data
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output access_out;// output data valid
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// control interface
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input load; // load parallel data (priority)
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input shift; // shift data
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input [CW-1:0] datasize; // size of data to to shift
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input lsbfirst; // lsb first order
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input fill; // fill bit
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input wait_in; // wait input
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output wait_out; // wait output (wait in | serial wait)
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//###########################
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//# BODY
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//###########################
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reg [PW-1:0] shiftreg;
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reg [CW-1:0] count;
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//##########################
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//# STATE MACHINE
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//##########################
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assign start_transfer = load &
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~wait_in;
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//transfer counter
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always @ (posedge clk or negedge nreset)
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if(~nreset)
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count[CW-1:0] <= 'b0;
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else if(start_transfer)
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count[CW-1:0] <= datasize[CW-1:0]; //1=1 byte
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else if(shift & busy)
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count[CW-1:0] <= count[CW-1:0] - 1'b1;
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assign access_out = (count[CW-1:0]==1'b1);
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//output data is valid while count>0
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assign busy = |count[CW-1:0];
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//wait until valid data is finished
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assign wait_out = (busy & ~access_out) |
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wait_in;
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//##########################
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//# SHIFT REGISTER
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//##########################
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always @ (posedge clk)
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if(start_transfer)
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shiftreg[PW-1:0] = din[PW-1:0];
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else if(shift & lsbfirst)
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shiftreg[PW-1:0] = {{(SW){fill}}, shiftreg[PW-SW-1:SW]};
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else if(shift)
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shiftreg[PW-1:0] = {shiftreg[PW-SW-1:0],{(SW){fill}}};
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assign dout[SW-1:0] = lsbfirst ? shiftreg[SW-1:0] :
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shiftreg[PW-1:PW-SW];
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endmodule // oh_par2ser
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///////////////////////////////////////////////////////////////////////////////
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// The MIT License (MIT) //
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// //
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// Copyright (c) 2015-2016, Adapteva, Inc. //
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// //
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// Permission is hereby granted, free of charge, to any person obtaining a //
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// copy of this software and associated documentation files (the "Software") //
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// to deal in the Software without restriction, including without limitation //
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// the rights to use, copy, modify, merge, publish, distribute, sublicense, //
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// and/or sell copies of the Software, and to permit persons to whom the //
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// Software is furnished to do so, subject to the following conditions: //
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// //
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// The above copyright notice and this permission notice shall be included //
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// in all copies or substantial portions of the Software. //
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// //
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS //
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// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF //
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// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. //
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// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY //
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// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT //
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// OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR //
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// THE USE OR OTHER DEALINGS IN THE SOFTWARE. //
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// //
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///////////////////////////////////////////////////////////////////////////////
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