Andreas Olofsson d8b5fa78ef Adding emesh as basic building block

2015-05-05 21:38:41 -04:00

..

ecfg_clocks.v

MILESTONE: Read/write works back and forth

2015-05-04 17:13:51 -04:00

ecfg_if.v

Adding emesh as basic building block

2015-05-05 21:38:41 -04:00

eclocks.v

MILESTONE: Read/write works back and forth

2015-05-04 17:13:51 -04:00

elink_constants.v

Adding constants to handle model

2015-05-02 21:30:26 -04:00

elink_example.v

Adding example design for FPGA

2015-05-05 21:37:17 -04:00

elink_regmap.v

MILESTONE: register read/write working!

2015-05-04 10:49:17 -04:00

elink.v

Adding emesh as basic building block

2015-05-05 21:38:41 -04:00

emaxi.v

Bug fix, missing pipeline stage on read response

2015-04-21 17:14:30 -04:00

ememory.v

Memory bug fix

2015-04-26 08:29:50 -04:00

ereset.v

Cleanup

2015-05-01 17:31:45 -04:00

erx_cfg.v

Renaming for my sanity (etx/erx split)

2015-05-05 14:56:35 -04:00

erx_disty.v

MILESTONE: Read/write works back and forth

2015-05-04 17:13:51 -04:00

erx_io.v

MILESTONE: Read/write works back and forth

2015-05-04 17:13:51 -04:00

erx_protocol.v

Adding emesh as basic building block

2015-05-05 21:38:41 -04:00

erx_remap.v

MILESTONE: Read/write works back and forth

2015-05-04 17:13:51 -04:00

erx_timer.v

Adding timeout circuit

2015-04-27 16:02:15 -04:00

erx.v

Renaming for my sanity (etx/erx split)

2015-05-05 14:56:35 -04:00

esaxi.v

File cleanup

2015-04-23 18:10:07 -04:00

etx_arbiter.v

MILESTONE: Read/write works back and forth

2015-05-04 17:13:51 -04:00

etx_cfg.v

Renaming for my sanity (etx/erx split)

2015-05-05 14:56:35 -04:00

etx_io.v

MILESTONE: Read/write works back and forth

2015-05-04 17:13:51 -04:00

etx_protocol.v

Baking in the IO wait signal into rd/wr wait

2015-05-04 17:10:32 -04:00

etx_remap.v

Separate rd/wr stalls

2015-05-04 17:09:50 -04:00

etx.v

Renaming for my sanity (etx/erx split)

2015-05-05 14:56:35 -04:00