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361 lines
14 KiB
Verilog
361 lines
14 KiB
Verilog
/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Fred Huettig <fred@adapteva.com>
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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module erx (/*AUTOARG*/
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// Outputs
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ecfg_rx_debug_signals, ecfg_datain, emaxi_emwr_empty,
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emaxi_emwr_rd_data, emaxi_emrq_empty, emaxi_emrq_rd_data,
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esaxi_emrr_empty, esaxi_emrr_rd_data, rx_wr_wait_p, rx_wr_wait_n,
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rx_rd_wait_p, rx_rd_wait_n, mi_data_out,
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// Inputs
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reset, s_axi_aclk, m_axi_aclk, ecfg_rx_enable, ecfg_rx_mmu_mode,
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ecfg_rx_gpio_mode, ecfg_dataout, emaxi_emwr_rd_en,
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emaxi_emrq_rd_en, esaxi_emrr_rd_en, rx_lclk_p, rx_lclk_n,
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rx_frame_p, rx_frame_n, rx_data_p, rx_data_n, mi_access, mi_addr,
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mi_data_in, mi_write
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);
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//Clocks and reset
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input reset;
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input s_axi_aclk; //clock for slave read request and write fifos
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input m_axi_aclk; //clock for master read response fifo
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//Configuration signals
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input ecfg_rx_enable;
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input ecfg_rx_mmu_mode;
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//Testing
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output [15:0] ecfg_rx_debug_signals; //various debug signals
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//GPIO mode
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input ecfg_rx_gpio_mode;
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input [10:0] ecfg_dataout;
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output [8:0] ecfg_datain;
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//Writes (to axi master)
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input emaxi_emwr_rd_en;
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output emaxi_emwr_empty;
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output [102:0] emaxi_emwr_rd_data;
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//Read requests (to axi master)
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input emaxi_emrq_rd_en;
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output emaxi_emrq_empty;
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output [102:0] emaxi_emrq_rd_data;
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//Read responses (to slave)
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input esaxi_emrr_rd_en;
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output esaxi_emrr_empty;
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output [102:0] esaxi_emrr_rd_data;
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//Transmit signals for IO
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input rx_lclk_p; //link clock output (up to 500MHz)
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input rx_lclk_n;
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input rx_frame_p; //transaction frame signal
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input rx_frame_n;
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input [7:0] rx_data_p; //transmit data (dual data rate)
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input [7:0] rx_data_n;
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output rx_wr_wait_p; //incoming pushback on write transactions
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output rx_wr_wait_n;
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output rx_rd_wait_p; //incoming pushback on read transactions
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output rx_rd_wait_n;
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//Write interface for MMU
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input mi_clk;
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input mi_en;
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input mi_we; //Single we, must write full words!
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input [RFAW-1:0] mi_addr;
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input [31:0] mi_din;
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output [31:0] mi_dout;
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/*AUTOOUTPUT*/
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire emesh_mmu_access; // From emmu of emmu.v
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wire [3:0] emesh_mmu_ctrlmode; // From emmu of emmu.v
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wire [DW-1:0] emesh_mmu_data; // From emmu of emmu.v
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wire [1:0] emesh_mmu_datamode; // From emmu of emmu.v
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wire [63:0] emesh_mmu_dstaddr; // From emmu of emmu.v
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wire [AW-1:0] emesh_mmu_srcaddr; // From emmu of emmu.v
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wire emesh_mmu_write; // From emmu of emmu.v
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wire emesh_rx_access; // From erx_protocol of erx_protocol.v
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wire [3:0] emesh_rx_ctrlmode; // From erx_protocol of erx_protocol.v
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wire [31:0] emesh_rx_data; // From erx_protocol of erx_protocol.v
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wire [1:0] emesh_rx_datamode; // From erx_protocol of erx_protocol.v
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wire [31:0] emesh_rx_dstaddr; // From erx_protocol of erx_protocol.v
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wire emesh_rx_rd_wait; // From erx_disty of erx_disty.v
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wire [31:0] emesh_rx_srcaddr; // From erx_protocol of erx_protocol.v
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wire emesh_rx_wr_wait; // From erx_disty of erx_disty.v
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wire emesh_rx_write; // From erx_protocol of erx_protocol.v
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wire emrq_full; // From m_rq_fifo of fifo_103x32.v
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wire emrq_prog_full; // From m_rq_fifo of fifo_103x32.v
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wire [102:0] emrq_wr_data; // From erx_disty of erx_disty.v
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wire emrq_wr_en; // From erx_disty of erx_disty.v
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wire emrr_full; // From s_rr_fifo of fifo_103x32.v
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wire emrr_prog_full; // From s_rr_fifo of fifo_103x32.v
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wire [102:0] emrr_wr_data; // From erx_disty of erx_disty.v
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wire emrr_wr_en; // From erx_disty of erx_disty.v
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wire emwr_full; // From m_wr_fifo of fifo_103x32.v
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wire emwr_prog_full; // From m_wr_fifo of fifo_103x32.v
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wire [102:0] emwr_wr_data; // From erx_disty of erx_disty.v
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wire emwr_wr_en; // From erx_disty of erx_disty.v
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wire rx_rd_wait; // From erx_protocol of erx_protocol.v
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wire rx_wr_wait; // From erx_protocol of erx_protocol.v
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wire [63:0] rxdata_p; // From erx_io of erx_io.v
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wire [7:0] rxframe_p; // From erx_io of erx_io.v
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wire rxlclk_p; // From erx_io of erx_io.v
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// End of automatics
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/************************************************************/
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/*FIFOs */
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/************************************************************/
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/*fifo_103x32 AUTO_TEMPLATE (
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.dout (e@"(substring vl-cell-name 0 1)"axi_em@"(substring vl-cell-name 2 4)"_rd_data[]),
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.empty (e@"(substring vl-cell-name 0 1)"axi_em@"(substring vl-cell-name 2 4)"_empty),
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.prog_full(em@"(substring vl-cell-name 2 4)"_prog_full),
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.full (em@"(substring vl-cell-name 2 4)"_full),
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.rd_clk (@"(substring vl-cell-name 0 1)"_axi_aclk),
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.rd_en (e@"(substring vl-cell-name 0 1)"axi_em@"(substring vl-cell-name 2 4)"_rd_en),
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.din (em@"(substring vl-cell-name 2 4)"_wr_data[]),
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.wr_en (em@"(substring vl-cell-name 2 4)"_wr_en),
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.wr_clk (rxlclk_p),
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.rst (reset),
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);
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*/
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//Read request fifo (from slave)
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fifo_103x32 m_rq_fifo(/*AUTOINST*/
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// Outputs
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.dout (emaxi_emrq_rd_data[102:0]), // Templated
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.empty (emaxi_emrq_empty), // Templated
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.full (emrq_full), // Templated
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.prog_full (emrq_prog_full), // Templated
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// Inputs
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.din (emrq_wr_data[102:0]), // Templated
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.rd_clk (m_axi_aclk), // Templated
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.rd_en (emaxi_emrq_rd_en), // Templated
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.rst (reset), // Templated
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.wr_clk (rxlclk_p), // Templated
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.wr_en (emrq_wr_en)); // Templated
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//Write fifo (from slave)
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fifo_103x32 m_wr_fifo(/*AUTOINST*/
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// Outputs
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.dout (emaxi_emwr_rd_data[102:0]), // Templated
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.empty (emaxi_emwr_empty), // Templated
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.full (emwr_full), // Templated
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.prog_full (emwr_prog_full), // Templated
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// Inputs
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.din (emwr_wr_data[102:0]), // Templated
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.rd_clk (m_axi_aclk), // Templated
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.rd_en (emaxi_emwr_rd_en), // Templated
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.rst (reset), // Templated
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.wr_clk (rxlclk_p), // Templated
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.wr_en (emwr_wr_en)); // Templated
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//Read response fifo (from master)
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fifo_103x32 s_rr_fifo(/*AUTOINST*/
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// Outputs
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.dout (esaxi_emrr_rd_data[102:0]), // Templated
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.empty (esaxi_emrr_empty), // Templated
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.full (emrr_full), // Templated
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.prog_full (emrr_prog_full), // Templated
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// Inputs
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.din (emrr_wr_data[102:0]), // Templated
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.rd_clk (s_axi_aclk), // Templated
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.rd_en (esaxi_emrr_rd_en), // Templated
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.rst (reset), // Templated
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.wr_clk (rxlclk_p), // Templated
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.wr_en (emrr_wr_en)); // Templated
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/************************************************************/
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/*ELINK RECEIVE DISTRIBUTOR ("DEMUX") */
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/*-sends transactin to the correct AXI channel fifo */
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/********************1***************************************/
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/*erx_disty AUTO_TEMPLATE (
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//Inputs
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.emesh_rd_wait (emesh_rx_rd_wait),
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.emesh_wr_wait (emesh_rx_wr_wait),
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.emesh_\(.*\) (emesh_mmu_\1[]),
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);
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*/
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erx_disty erx_disty (
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/*AUTOINST*/
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// Outputs
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.emesh_rd_wait (emesh_rx_rd_wait), // Templated
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.emesh_wr_wait (emesh_rx_wr_wait), // Templated
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.emwr_wr_data (emwr_wr_data[102:0]),
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.emwr_wr_en (emwr_wr_en),
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.emrq_wr_data (emrq_wr_data[102:0]),
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.emrq_wr_en (emrq_wr_en),
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.emrr_wr_data (emrr_wr_data[102:0]),
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.emrr_wr_en (emrr_wr_en),
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// Inputs
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.rxlclk_p (rxlclk_p),
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.emesh_access (emesh_mmu_access), // Templated
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.emesh_write (emesh_mmu_write), // Templated
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.emesh_datamode (emesh_mmu_datamode[1:0]), // Templated
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.emesh_ctrlmode (emesh_mmu_ctrlmode[3:0]), // Templated
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.emesh_dstaddr (emesh_mmu_dstaddr[31:0]), // Templated
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.emesh_srcaddr (emesh_mmu_srcaddr[31:0]), // Templated
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.emesh_data (emesh_mmu_data[31:0]), // Templated
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.emwr_full (emwr_full),
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.emwr_prog_full (emwr_prog_full),
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.emrq_full (emrq_full),
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.emrq_prog_full (emrq_prog_full),
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.emrr_full (emrr_full),
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.emrr_prog_full (emrr_prog_full),
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.ecfg_rx_enable (ecfg_rx_enable));
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/************************************************************/
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/*ELINK MEMORY MANAGEMENT UNIT */
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/*-translates destination address */
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/************************************************************/
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/*emmu AUTO_TEMPLATE (
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// Outputs
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.emesh_\(.*\)_out (emesh_mmu_\1[]),
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//Inputs
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.emesh_\(.*\)_in (emesh_rx_\1[]),
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);
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*/
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emmu emmu (.clk (rxlclk_p),
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.mmu_en (ecfg_rx_mmu_mode),
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/*AUTOINST*/
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// Outputs
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.mi_data_out (mi_data_out[DW-1:0]),
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.emesh_access_out (emesh_mmu_access), // Templated
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.emesh_write_out (emesh_mmu_write), // Templated
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.emesh_datamode_out (emesh_mmu_datamode[1:0]), // Templated
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.emesh_ctrlmode_out (emesh_mmu_ctrlmode[3:0]), // Templated
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.emesh_dstaddr_out (emesh_mmu_dstaddr[63:0]), // Templated
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.emesh_srcaddr_out (emesh_mmu_srcaddr[AW-1:0]), // Templated
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.emesh_data_out (emesh_mmu_data[DW-1:0]), // Templated
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// Inputs
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.mi_access (mi_access),
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.mi_write (mi_write),
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.mi_addr (mi_addr[IW:0]),
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.mi_data_in (mi_data_in[DW-1:0]),
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.emesh_access_in (emesh_rx_access), // Templated
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.emesh_write_in (emesh_rx_write), // Templated
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.emesh_datamode_in (emesh_rx_datamode[1:0]), // Templated
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.emesh_ctrlmode_in (emesh_rx_ctrlmode[3:0]), // Templated
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.emesh_dstaddr_in (emesh_rx_dstaddr[AW-1:0]), // Templated
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.emesh_srcaddr_in (emesh_rx_srcaddr[AW-1:0]), // Templated
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.emesh_data_in (emesh_rx_data[DW-1:0])); // Templated
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/************************************************************/
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/*ELINK PROTOCOL LOGIC */
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/*-translates the elink packet to 104 bit emesh bits */
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/************************************************************/
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erx_protocol erx_protocol (/*AUTOINST*/
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// Outputs
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.rx_rd_wait (rx_rd_wait),
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.rx_wr_wait (rx_wr_wait),
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.emesh_rx_access (emesh_rx_access),
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.emesh_rx_write (emesh_rx_write),
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.emesh_rx_datamode(emesh_rx_datamode[1:0]),
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.emesh_rx_ctrlmode(emesh_rx_ctrlmode[3:0]),
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.emesh_rx_dstaddr (emesh_rx_dstaddr[31:0]),
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.emesh_rx_srcaddr (emesh_rx_srcaddr[31:0]),
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.emesh_rx_data (emesh_rx_data[31:0]),
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// Inputs
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.reset (reset),
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.rxlclk_p (rxlclk_p),
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.rxframe_p (rxframe_p[7:0]),
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.rxdata_p (rxdata_p[63:0]),
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.emesh_rx_rd_wait (emesh_rx_rd_wait),
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.emesh_rx_wr_wait (emesh_rx_wr_wait));
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/***********************************************************/
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/*ELINK TRANSMIT I/O LOGIC */
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/*-parallel data and frame as input */
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/*-serializes data for I/O */
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/***********************************************************/
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erx_io erx_io (.ioreset (reset),
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.txlclk_p (1'b0),//TODO
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/*AUTOINST*/
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// Outputs
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.rx_wr_wait_p (rx_wr_wait_p),
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.rx_wr_wait_n (rx_wr_wait_n),
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.rx_rd_wait_p (rx_rd_wait_p),
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.rx_rd_wait_n (rx_rd_wait_n),
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.rxlclk_p (rxlclk_p),
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.rxframe_p (rxframe_p[7:0]),
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.rxdata_p (rxdata_p[63:0]),
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.ecfg_datain (ecfg_datain[8:0]),
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// Inputs
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.rx_lclk_p (rx_lclk_p),
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.rx_lclk_n (rx_lclk_n),
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.reset (reset),
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.rx_frame_p (rx_frame_p),
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.rx_frame_n (rx_frame_n),
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.rx_data_p (rx_data_p[7:0]),
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.rx_data_n (rx_data_n[7:0]),
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.rx_wr_wait (rx_wr_wait),
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.rx_rd_wait (rx_rd_wait),
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.ecfg_rx_enable (ecfg_rx_enable),
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.ecfg_rx_gpio_mode (ecfg_rx_gpio_mode),
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.ecfg_dataout (ecfg_dataout[10:0]));
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/************************************************************/
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/*Debug signals */
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/************************************************************/
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always @ (posedge rxlclk_p)
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begin
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ecfg_rx_debug_signals[15:0] <= {2'b0, //15:14
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emesh_rx_rd_wait, //13
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emesh_rx_wr_wait, //12
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esaxi_emrr_rd_en, //11
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emrr_full, //10
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emrr_prog_full, //9
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emrr_wr_en, //8
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emaxi_emrq_rd_en, //7
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emrq_full, //6
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emrq_prog_full, //5
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emrq_wr_en, //4
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emaxi_emwr_rd_en, //3
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emwr_full, //2
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emwr_prog_full, //1
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emwr_wr_en //0
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};
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end
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endmodule // elink
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// Local Variables:
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// verilog-library-directories:("." "../../stubs/hdl" "../../emmu/hdl")
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// End:
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