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347 lines
12 KiB
Verilog
347 lines
12 KiB
Verilog
/*
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File: e_rx_io.v
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This file is part of the Parallella Project .
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Fred Huettig <fred@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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module erx_io (/*AUTOARG*/
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// Outputs
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rx_wr_wait_p, rx_wr_wait_n, rx_rd_wait_p, rx_rd_wait_n, rxlclk_p,
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rxframe_p, rxdata_p, ecfg_datain,
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// Inputs
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rx_lclk_p, rx_lclk_n, reset, ioreset, rx_frame_p, rx_frame_n,
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rx_data_p, rx_data_n, rx_wr_wait, rx_rd_wait, ecfg_rx_enable,
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ecfg_rx_gpio_mode, ecfg_dataout
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);
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parameter IOSTD_ELINK = "LVDS_25";
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//###########
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//# eLink pins
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//###########
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input rx_lclk_p, rx_lclk_n; // Differential clock from IOB
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input reset;
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input ioreset;
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input rx_frame_p, rx_frame_n; // Inputs from eLink
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input [7:0] rx_data_p, rx_data_n;
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output rx_wr_wait_p, rx_wr_wait_n;
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output rx_rd_wait_p, rx_rd_wait_n;
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//#############
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//# Fabric interface, 1/8 bit rate of eLink
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//#############
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output rxlclk_p; // Parallel clock output (slow)
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output [7:0] rxframe_p;
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output [63:0] rxdata_p;
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input rx_wr_wait;
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input rx_rd_wait;
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//#############
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//# Configuration bits
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//#############
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input ecfg_rx_enable; //enable signal for rx
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input ecfg_rx_gpio_mode; //forces rx wait pins to constants
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input [10:0] ecfg_dataout; // rd_wait, wr_wait for GPIO mode
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output [8:0] ecfg_datain; //gpio data in (data in and frame)
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//############
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//# REGS
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//############
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reg [63:0] rxdata_p; // output registers
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reg [7:0] rxframe_p;
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//############
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//# WIRES
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//############
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wire [7:0] rx_data; // High-speed serial data
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wire rx_frame; // serial frame
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wire serdes_reset;
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//################################
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//# Input Buffers Instantiation
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//################################
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IBUFDS
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#(.DIFF_TERM ("TRUE"), // Differential termination
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.IOSTANDARD (IOSTD_ELINK))
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ibufds_rxdata[0:7]
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(.I (rx_data_p),
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.IB (rx_data_n),
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.O (rx_data));
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IBUFDS
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#(.DIFF_TERM ("TRUE"), // Differential termination
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.IOSTANDARD (IOSTD_ELINK))
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ibufds_rxframe
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(.I (rx_frame_p),
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.IB (rx_frame_n),
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.O (rx_frame));
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//#####################
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//# Clock Buffers
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//#####################
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wire rx_lclk; // Single-ended clock
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wire rx_lclk_s; // Serial clock after BUFIO
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IBUFGDS
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#(.DIFF_TERM ("TRUE"), // Differential termination
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.IOSTANDARD (IOSTD_ELINK))
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ibufds_rxlclk
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(.I (rx_lclk_p),
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.IB (rx_lclk_n),
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.O (rx_lclk));
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BUFIO bufio_rxlclk
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(.I (rx_lclk),
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.O (rx_lclk_s));
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// BUFR generates the slow clock
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BUFR
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#(.SIM_DEVICE("7SERIES"),
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.BUFR_DIVIDE("4"))
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clkout_bufr
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(.O (rxlclk_p),
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.CE(1'b1),
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.CLR(1'b0),
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.I (rx_lclk));
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//#############################
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//# Deserializer instantiations
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//#############################
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wire [63:0] rxdata_des;
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wire [7:0] rxframe_des;
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wire rx_lclk_sn = ~rx_lclk_s;
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genvar i;
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generate for(i=0; i<8; i=i+1)
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begin : gen_serdes
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ISERDESE2
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#(
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.DATA_RATE("DDR"), // DDR, SDR
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.DATA_WIDTH(8), // Parallel data width (2-8,10,14)
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.DYN_CLKDIV_INV_EN("FALSE"), // Enable DYNCLKDIVINVSEL inversion (FALSE, TRUE)
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.DYN_CLK_INV_EN("FALSE"), // Enable DYNCLKINVSEL inversion (FALSE, TRUE)
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// INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
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.INIT_Q1(1'b0),
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.INIT_Q2(1'b0),
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.INIT_Q3(1'b0),
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.INIT_Q4(1'b0),
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.INTERFACE_TYPE("NETWORKING"),
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// MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE
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.IOBDELAY("NONE"), // NONE, BOTH, IBUF, IFD
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.NUM_CE(2), // Number of clock enables (1,2)
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.OFB_USED("FALSE"), // Select OFB path (FALSE, TRUE)
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.SERDES_MODE("MASTER"), // MASTER, SLAVE
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// SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
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.SRVAL_Q1(1'b0),
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.SRVAL_Q2(1'b0),
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.SRVAL_Q3(1'b0),
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.SRVAL_Q4(1'b0)
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)
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ISERDESE2_rxdata
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(
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.O(), // 1-bit output: Combinatorial output
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// Q1 - Q8: 1-bit (each) output: Registered data outputs
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.Q1(rxdata_des[i]), // Last data in?
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.Q2(rxdata_des[i+8]),
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.Q3(rxdata_des[i+16]),
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.Q4(rxdata_des[i+24]),
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.Q5(rxdata_des[i+32]),
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.Q6(rxdata_des[i+40]),
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.Q7(rxdata_des[i+48]),
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.Q8(rxdata_des[i+56]), // First data in?
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// SHIFTOUT1, SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
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.SHIFTOUT1(),
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.SHIFTOUT2(),
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.BITSLIP(1'b0), // 1-bit input: The BITSLIP pin performs a Bitslip operation
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// synchronous to CLKDIV when asserted (active High). Subsequently, the data
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// seen on the Q1 to Q8 output ports will shift, as in a barrel-shifter
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// operation, one position every time Bitslip is invoked. DDR operation is
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// different from SDR.
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// CE1, CE2: 1-bit (each) input: Data register clock enable inputs
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.CE1(1'b1),
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.CE2(1'b1),
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.CLKDIVP(1'b0), // 1-bit input: TBD
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// Clocks: 1-bit (each) input: ISERDESE2 clock input ports
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.CLK(rx_lclk_s), // 1-bit input: High-speed clock
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.CLKB(rx_lclk_sn), // 1-bit input: High-speed secondary clock
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.CLKDIV(rxlclk_p), // 1-bit input: Divided clock
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.OCLK(1'b0), // 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY"
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// Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity
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.DYNCLKDIVSEL(1'b0), // 1-bit input: Dynamic CLKDIV inversion
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.DYNCLKSEL(1'b0), // 1-bit input: Dynamic CLK/CLKB inversion
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// Input Data: 1-bit (each) input: ISERDESE2 data input ports
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.D(rx_data[i]), // 1-bit input: Data input
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.DDLY(1'b0), // 1-bit input: Serial data from IDELAYE2
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.OFB(1'b0), // 1-bit input: Data feedback from OSERDESE2
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.OCLKB(1'b0), // 1-bit input: High speed negative edge output clock
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.RST(serdes_reset), // 1-bit input: Active high asynchronous reset
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// SHIFTIN1, SHIFTIN2: 1-bit (each) input: Data width expansion input ports
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.SHIFTIN1(1'b0),
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.SHIFTIN2(1'b0)
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);
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end // block: gen_serdes
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endgenerate
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ISERDESE2
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#(
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.DATA_RATE("DDR"), // DDR, SDR
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.DATA_WIDTH(8), // Parallel data width (2-8,10,14)
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.DYN_CLKDIV_INV_EN("FALSE"), // Enable DYNCLKDIVINVSEL inversion (FALSE, TRUE)
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.DYN_CLK_INV_EN("FALSE"), // Enable DYNCLKINVSEL inversion (FALSE, TRUE)
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// INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
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.INIT_Q1(1'b0),
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.INIT_Q2(1'b0),
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.INIT_Q3(1'b0),
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.INIT_Q4(1'b0),
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.INTERFACE_TYPE("NETWORKING"),
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// MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE
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.IOBDELAY("NONE"), // NONE, BOTH, IBUF, IFD
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.NUM_CE(2), // Number of clock enables (1,2)
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.OFB_USED("FALSE"), // Select OFB path (FALSE, TRUE)
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.SERDES_MODE("MASTER"), // MASTER, SLAVE
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// SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
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.SRVAL_Q1(1'b0),
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.SRVAL_Q2(1'b0),
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.SRVAL_Q3(1'b0),
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.SRVAL_Q4(1'b0)
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)
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ISERDESE2_rxframe
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(
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.O(), // 1-bit output: Combinatorial output
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// Q1 - Q8: 1-bit (each) output: Registered data outputs
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.Q1(rxframe_des[0]),
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.Q2(rxframe_des[1]),
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.Q3(rxframe_des[2]),
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.Q4(rxframe_des[3]),
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.Q5(rxframe_des[4]),
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.Q6(rxframe_des[5]),
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.Q7(rxframe_des[6]),
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.Q8(rxframe_des[7]),
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// SHIFTOUT1, SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
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.SHIFTOUT1(),
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.SHIFTOUT2(),
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.BITSLIP(1'b0), // 1-bit input: The BITSLIP pin performs a Bitslip operation
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// synchronous to CLKDIV when asserted (active High). Subsequently, the data
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// seen on the Q1 to Q8 output ports will shift, as in a barrel-shifter
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// operation, one position every time Bitslip is invoked. DDR operation is
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// different from SDR.
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// CE1, CE2: 1-bit (each) input: Data register clock enable inputs
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.CE1(1'b1),
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.CE2(1'b1),
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.CLKDIVP(1'b0), // 1-bit input: TBD
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// Clocks: 1-bit (each) input: ISERDESE2 clock input ports
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.CLK(rx_lclk_s), // 1-bit input: High-speed clock
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.CLKB(rx_lclk_sn), // 1-bit input: High-speed secondary clock
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.CLKDIV(rxlclk_p), // 1-bit input: Divided clock
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.OCLK(1'b0), // 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY"
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// Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity
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.DYNCLKDIVSEL(1'b0), // 1-bit input: Dynamic CLKDIV inversion
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.DYNCLKSEL(1'b0), // 1-bit input: Dynamic CLK/CLKB inversion
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// Input Data: 1-bit (each) input: ISERDESE2 data input ports
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.D(rx_frame), // 1-bit input: Data input
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.DDLY(1'b0), // 1-bit input: Serial data from IDELAYE2
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.OFB(1'b0), // 1-bit input: Data feedback from OSERDESE2
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.OCLKB(1'b0), // 1-bit input: High speed negative edge output clock
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.RST(serdes_reset), // 1-bit input: Active high asynchronous reset
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// SHIFTIN1, SHIFTIN2: 1-bit (each) input: Data width expansion input ports
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.SHIFTIN1(1'b0),
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.SHIFTIN2(1'b0)
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);
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// Sync control signals into our RX clock domain
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reg [1:0] rxenb_sync;
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wire rxenb = rxenb_sync[0];
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assign serdes_reset = ~rxenb;
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reg [1:0] rxgpio_sync;
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wire rxgpio = rxgpio_sync[0];
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// Register outputs once for good measure, then mux in loopback data if enabled
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reg [63:0] rxdata_reg;
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reg [7:0] rxframe_reg;
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wire rxreset = reset | ~ecfg_rx_enable;
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always @ (posedge rxlclk_p or posedge rxreset) begin
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if(rxreset)
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rxenb_sync <= 'd0;
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else
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rxenb_sync <= {1'b1, rxenb_sync[1]};
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end
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always @ (posedge rxlclk_p) begin
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rxgpio_sync <= {ecfg_rx_gpio_mode, rxgpio_sync[1]};
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rxdata_reg <= rxdata_des;
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rxframe_reg <= rxframe_des & {8{rxenb}} & {8{~rxgpio}};
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rxdata_p <= rxdata_reg;
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rxframe_p <= rxframe_reg;
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end
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end // always @ (posedge rxlclk_p)
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//#############
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//# GPIO mode inputs
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//#############
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reg [8:0] datain_reg;
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reg [8:0] ecfg_datain;
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always @ (posedge rxlclk_p)
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begin
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datain_reg[8] <= rxframe_p[0];
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datain_reg[7:0] <= rxdata_p[7:0];
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ecfg_datain[8:0] <= datain_reg[8:0];
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end
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//#############
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//# Wait signals (asynchronous)
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//#############
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wire wr_wait = rxgpio ? ecfg_dataout[9] : rx_wr_wait;
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wire rd_wait = rxgpio ? ecfg_dataout[10] : rx_rd_wait;
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OBUFDS
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#(
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.IOSTANDARD(IOSTD_ELINK),
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.SLEW("SLOW")
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) OBUFDS_RXWRWAIT
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(
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.O(rx_wr_wait_p),
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.OB(rx_wr_wait_n),
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.I(wr_wait)
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);
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OBUFDS
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#(
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.IOSTANDARD(IOSTD_ELINK),
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.SLEW("SLOW")
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) OBUFDS_RXRDWAIT
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(
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.O(rx_rd_wait_p),
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.OB(rx_rd_wait_n),
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.I(rd_wait)
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);
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endmodule // e_rx_io
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