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Andreas Olofsson 4fb6e7407c Integrating idelay elements in erx_io
2015-05-16 22:06:40 -04:00
common
Changing default to simplify instantiation
2015-05-14 22:46:23 -04:00
edma
Making dma quiet until implemented
2015-05-03 23:23:02 -04:00
elink
Integrating idelay elements in erx_io
2015-05-16 22:06:40 -04:00
emailbox
Making FIFO/memories easier to use
2015-05-07 23:50:34 -04:00
emesh/hdl
Fixing syntax errors caught in synthesis
2015-05-06 12:27:13 -04:00
emmu
Separating rd/wr wait for pipeline stall
2015-05-04 17:09:23 -04:00
memory
Adding reset to both sides of fifo
2015-05-14 22:47:25 -04:00
xilibs
Adding IDDR model
2015-05-15 15:27:45 -04:00
.gitignore
Adding register access from RX
2015-04-27 23:51:00 -04:00
CONTRIBUTING.md
Basic infrastructure
2015-04-21 21:36:37 -04:00
COPYING
Basic infrastructure
2015-04-21 21:36:37 -04:00
LICENSE
Initial commit
2015-04-21 21:16:42 -04:00
README.md
Massive commit sequence coming...
2015-04-23 17:48:12 -04:00

README.md

=======

OH!

Open Hardware (Pure and Simple)

(work in progress...)

Description
No description provided
Readme MIT 43 MiB
Languages
Verilog 81.1%
Tcl 10.7%
C 5.6%
Shell 0.8%
Python 0.6%
Other 1.2%