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207 lines
6.7 KiB
Verilog
207 lines
6.7 KiB
Verilog
//#############################################################################
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//# Purpose: "Mini-IO" (MIO) #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module mio #( parameter IOW = 64, // IO width
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parameter AW = 32, // address width
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parameter PW = 104, // emesh packet width
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parameter DEF_CFG = 18'h0010, // default config
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parameter DEF_CLK = 7, // clock divider
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parameter TARGET = "GENERIC" // GENERIC,XILINX,ALTERA,GENERIC,ASIC
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)
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(// reset, clk, config
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input clk, // main core clock
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input nreset, // async active low reset
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// io chip interface
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output tx_clk, // phase shited io_clk
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output tx_access, // access signal for IO
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output [IOW-1:0] tx_packet, // packet for IO
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input tx_wait, // pushback from IO
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input rx_clk, // rx clock
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input rx_access, // rx access
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input [IOW-1:0] rx_packet, // rx packet
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output rx_wait, // pushback from IO
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// mesh interface
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input access_in, // access for tx
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input [PW-1:0] packet_in, // access for tx
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output wait_out, // access from tx fifo
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output access_out, // access from rx
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output [PW-1:0] packet_out, // packet from rx
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input wait_in, // pushback for rx fifo
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// register interface
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input reg_access_in, // config register access
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input [PW-1:0] reg_packet_in, // config register packet
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output reg_wait_out, // pushback by register read
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output reg_access_out,// config readback
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output [PW-1:0] reg_packet_out,// config reacback packet
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input reg_wait_in // pushback for readback
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);
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// local wires
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wire io_clk;
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// End of automatics
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire amode; // From mio_regs of mio_regs.v
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wire clkchange; // From mio_regs of mio_regs.v
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wire [7:0] clkdiv; // From mio_regs of mio_regs.v
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wire [15:0] clkphase0; // From mio_regs of mio_regs.v
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wire [15:0] clkphase1; // From mio_regs of mio_regs.v
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wire [4:0] ctrlmode; // From mio_regs of mio_regs.v
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wire [1:0] datamode; // From mio_regs of mio_regs.v
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wire ddr_mode; // From mio_regs of mio_regs.v
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wire dmode; // From mio_regs of mio_regs.v
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wire [AW-1:0] dstaddr; // From mio_regs of mio_regs.v
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wire emode; // From mio_regs of mio_regs.v
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wire framepol; // From mio_regs of mio_regs.v
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wire [1:0] iowidth; // From mio_regs of mio_regs.v
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wire lsbfirst; // From mio_regs of mio_regs.v
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wire rx_empty; // From mrx of mrx.v
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wire rx_en; // From mio_regs of mio_regs.v
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wire rx_full; // From mrx of mrx.v
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wire rx_prog_full; // From mrx of mrx.v
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wire tx_empty; // From mtx of mtx.v
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wire tx_en; // From mio_regs of mio_regs.v
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wire tx_full; // From mtx of mtx.v
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wire tx_prog_full; // From mtx of mtx.v
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// End of automatics
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//################################
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//# TRANSMIT
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//################################
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mtx #(.IOW(IOW),
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.AW(AW),
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.PW(PW),
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.TARGET(TARGET))
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mtx (.io_clk (io_clk),
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/*AUTOINST*/
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// Outputs
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.tx_empty (tx_empty),
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.tx_full (tx_full),
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.tx_prog_full (tx_prog_full),
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.wait_out (wait_out),
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.tx_access (tx_access),
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.tx_packet (tx_packet[IOW-1:0]),
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// Inputs
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.clk (clk),
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.nreset (nreset),
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.tx_en (tx_en),
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.ddr_mode (ddr_mode),
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.lsbfirst (lsbfirst),
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.emode (emode),
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.iowidth (iowidth[1:0]),
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.access_in (access_in),
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.packet_in (packet_in[PW-1:0]),
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.tx_wait (tx_wait));
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//################################
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//# RECEIVE
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//################################
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mrx #(.IOW(IOW),
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.AW(AW),
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.PW(PW),
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.TARGET(TARGET))
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mrx (/*AUTOINST*/
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// Outputs
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.rx_empty (rx_empty),
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.rx_full (rx_full),
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.rx_prog_full (rx_prog_full),
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.rx_wait (rx_wait),
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.access_out (access_out),
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.packet_out (packet_out[PW-1:0]),
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// Inputs
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.clk (clk),
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.nreset (nreset),
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.ddr_mode (ddr_mode),
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.iowidth (iowidth[1:0]),
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.amode (amode),
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.ctrlmode (ctrlmode[4:0]),
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.datamode (datamode[1:0]),
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.dstaddr (dstaddr[AW-1:0]),
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.emode (emode),
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.rx_clk (rx_clk),
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.rx_access (rx_access),
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.rx_packet (rx_packet[IOW-1:0]),
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.wait_in (wait_in));
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//################################
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//# MIO Control Registers
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//################################
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/*mio_regs AUTO_TEMPLATE (.\(.*\)_out (reg_\1_out[]),
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.\(.*\)_in (reg_\1_in[]),
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);
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*/
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mio_regs #(.AW(AW),
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.PW(PW),
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.DEF_CFG(DEF_CFG),
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.DEF_CLK(DEF_CLK))
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mio_regs (/*AUTOINST*/
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// Outputs
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.wait_out (reg_wait_out), // Templated
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.access_out (reg_access_out), // Templated
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.packet_out (reg_packet_out[PW-1:0]), // Templated
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.tx_en (tx_en),
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.rx_en (rx_en),
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.ddr_mode (ddr_mode),
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.emode (emode),
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.amode (amode),
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.dmode (dmode),
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.datamode (datamode[1:0]),
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.iowidth (iowidth[1:0]),
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.lsbfirst (lsbfirst),
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.framepol (framepol),
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.ctrlmode (ctrlmode[4:0]),
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.dstaddr (dstaddr[AW-1:0]),
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.clkchange (clkchange),
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.clkdiv (clkdiv[7:0]),
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.clkphase0 (clkphase0[15:0]),
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.clkphase1 (clkphase1[15:0]),
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// Inputs
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.clk (clk),
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.nreset (nreset),
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.access_in (reg_access_in), // Templated
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.packet_in (reg_packet_in[PW-1:0]), // Templated
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.wait_in (reg_wait_in), // Templated
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.tx_full (tx_full),
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.tx_prog_full (tx_prog_full),
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.tx_empty (tx_empty),
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.rx_full (rx_full),
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.rx_prog_full (rx_prog_full),
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.rx_empty (rx_empty));
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//################################
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//# TX CLOCK DRIVER
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//################################
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oh_clockdiv oh_clockdiv(.clkrise0 (),
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.clkfall0 (),
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.clkrise1 (),
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.clkfall1 (),
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.clkstable (),
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.clkout0 (io_clk),
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.clkout1 (tx_clk),
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.clken (tx_en),
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/*AUTOINST*/
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// Inputs
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.clk (clk),
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.nreset (nreset),
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.clkchange (clkchange),
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.clkdiv (clkdiv[7:0]),
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.clkphase0 (clkphase0[15:0]),
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.clkphase1 (clkphase1[15:0]));
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endmodule // mio
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// Local Variables:
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// verilog-library-directories:("." "../hdl" "../../common/hdl")
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// End:
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