mirror of
https://github.com/aolofsson/oh.git
synced 2025-01-30 02:32:53 +08:00
52b328c194
- Old design was not workable with bursting and long waits. The wait signal needs to be very carfully handled since it's asynchronous to the clock. -The TX needs to be stopped quickly so the sync needs to be done at the high speed clock, not at div4 clock -Since there are synchronizers here, there should be only one point of sync. This is not completely the case still, but I think??? it should be safe by constructiona at this point. -bursting working at this point for writes!!!!!
=======
OH!
An Open Hardware Library for Chip and FPGA designers written in Verilog
CONTENT
| Spec | Description |
|---|---|
| common | Common utility modules and scripts |
| edma | DMA module |
| emesh | Epiphany emesh related circuits |
| elink | Epiphany point to point LVDS link |
| emailbox | Simple mailbox with interrupt output |
| emmu | Simple memory transaction translation unit |
| memory | Various simple memory structures (RAM/FIFO) |
| xilibs | Simulation modules for Xilinx primitives |
LICENSE
The OH! repository source code is licensed under the MIT license unless otherwise specified. See LICENSE for full copyright terms.
CONTRIBUTING
Instructions for contributing can be found HERE.