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f7806821c7
- using rx reset, safer as this stays in reset longer, until the clock has hade time to clean up the rest
125 lines
3.3 KiB
Verilog
125 lines
3.3 KiB
Verilog
`include "elink_regmap.v"
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module erx_arbiter (/*AUTOARG*/
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// Outputs
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rx_rd_wait, rx_wr_wait, edma_wait, ecfg_wait, rxwr_access,
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rxwr_packet, rxrd_access, rxrd_packet, rxrr_access, rxrr_packet,
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// Inputs
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erx_rr_access, erx_packet, emmu_access, emmu_packet, edma_access,
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edma_packet, ecfg_access, ecfg_packet, timeout, rxwr_wait,
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rxrd_wait, rxrr_wait
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);
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parameter AW = 32;
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parameter DW = 32;
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parameter PW = 104;
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parameter ID = 12'h800; //link id
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parameter RFAW = 6;
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//From IO (for rr)
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input erx_rr_access;
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input [PW-1:0] erx_packet;
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output rx_rd_wait; //for IO
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output rx_wr_wait; //for IO
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//From EMMU (writes)
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input emmu_access;
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input [PW-1:0] emmu_packet;
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//From DMA
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input edma_access;
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input [PW-1:0] edma_packet;
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output edma_wait;
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//From ETX
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input ecfg_access;
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input [PW-1:0] ecfg_packet;
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output ecfg_wait;
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//From timeout circuit
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input timeout;
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//To Master Write FIFO
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output rxwr_access;
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output [PW-1:0] rxwr_packet;
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input rxwr_wait;
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//To Master Read FIFO
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output rxrd_access;
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output [PW-1:0] rxrd_packet;
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input rxrd_wait;
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//To Slave Read Response FIFO
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output rxrr_access;
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output [PW-1:0] rxrr_packet;
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input rxrr_wait;
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//####################################
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//Splicing pakets
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//####################################
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wire emmu_write;
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wire [AW-1:0] emmu_dstaddr;
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wire emmu_read;
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packet2emesh p2e (// Outputs
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.write_out (emmu_write),
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.datamode_out (),
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.ctrlmode_out (),
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.data_out (),
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.dstaddr_out (emmu_dstaddr[AW-1:0]),
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.srcaddr_out (),
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// Inputs
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.packet_in (emmu_packet[PW-1:0]));
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//#######################################################
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//Read response path (from IO or elink register readback)
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//#######################################################
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assign rxrr_access = erx_rr_access | ecfg_access;
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assign rxrr_packet[PW-1:0] = erx_rr_access ? erx_packet[PW-1:0] :
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ecfg_packet[PW-1:0];
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//####################################
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//Write Path (from IO through MMU)
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//####################################
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assign rxwr_access = emmu_access &
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emmu_write &
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~(emmu_dstaddr[31:20]==ID);
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assign rxwr_packet[PW-1:0] = emmu_packet[PW-1:0];
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//########################################
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//Read Request Path (from IO through MMU)
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//########################################
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assign emmu_read = emmu_access & ~emmu_write;
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assign rxrd_access = emmu_read | edma_access;
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assign rxrd_packet[PW-1:0] = emmu_read ? emmu_packet[PW-1:0] :
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edma_packet[PW-1:0];
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//####################################
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//Wait Signals
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//####################################
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assign rx_rd_wait = rxrd_wait;
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assign rx_wr_wait = rxwr_wait | (rxrr_wait & rxrr_access);
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assign edma_wait = rxrd_wait | emmu_read;
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assign ecfg_wait = erx_rr_access |
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rxrr_wait |
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rxwr_wait;
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endmodule // erx_arbiter
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// Local Variables:
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// verilog-library-directories:("." "../../common/hdl" "../../emesh/hdl")
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// End:
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