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376 lines
9.2 KiB
Verilog
376 lines
9.2 KiB
Verilog
/*
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This block receives the IO transaction and converts to a 104 bit packet.
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*/
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`include "elink_constants.v"
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module erx_io (/*AUTOARG*/
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// Outputs
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rx_lclk_pll, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p,
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rxo_rd_wait_n, rx_access, rx_burst, rx_packet,
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// Inputs
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reset, rx_lclk, rx_lclk_div4, rxi_lclk_p, rxi_lclk_n, rxi_frame_p,
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rxi_frame_n, rxi_data_p, rxi_data_n, rx_wr_wait, rx_rd_wait
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);
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parameter IOSTD_ELINK = "LVDS_25";
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parameter PW = 104;
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// Can we do this in a better way?
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//parameter [8:0] RX_TAP_DELAY [8:0];
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reg [3:0] RX_TAP_DELAY[8:0];
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initial
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begin
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RX_TAP_DELAY[0]=4'd15;
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RX_TAP_DELAY[1]=4'd15;
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RX_TAP_DELAY[2]=4'd15;
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RX_TAP_DELAY[3]=4'd15;
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RX_TAP_DELAY[4]=4'd14;
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RX_TAP_DELAY[5]=4'd15;
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RX_TAP_DELAY[6]=4'd14;
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RX_TAP_DELAY[7]=4'd15;
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RX_TAP_DELAY[8]=4'd14;
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end
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//#########################
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//# reset, clocks
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//#########################
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input reset; // reset
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input rx_lclk; // fast I/O clock
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input rx_lclk_div4; // slow clock
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output rx_lclk_pll; // clock output for pll
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//##########################
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//# elink pins
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//##########################
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input rxi_lclk_p, rxi_lclk_n; // rx clock input
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input rxi_frame_p, rxi_frame_n; // rx frame signal
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input [7:0] rxi_data_p, rxi_data_n; // rx data
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output rxo_wr_wait_p,rxo_wr_wait_n; // rx write pushback output
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output rxo_rd_wait_p,rxo_rd_wait_n; // rx read pushback output
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//##########################
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//# erx logic interface
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//##########################
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output rx_access;
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output rx_burst;
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output [PW-1:0] rx_packet;
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input rx_wr_wait;
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input rx_rd_wait;
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//############
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//# WIRES
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//############
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wire [7:0] rxi_data;
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wire rxi_frame;
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wire rxi_lclk;
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wire access_wide;
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reg valid_packet;
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wire [15:0] rx_word;
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reg [15:0] rx_word_sync;
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//############
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//# REGS
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//############
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reg [7:0] data_even_reg;
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reg [7:0] data_odd_reg;
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wire [1:0] rx_frame;
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reg [1:0] rx_frame_sync;
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wire rx_frame_old;
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reg [111:0] rx_sample;
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reg [6:0] rx_pointer;
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reg access;
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reg burst;
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reg [PW-1:0] rx_packet_lclk;
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reg rx_access;
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reg [PW-1:0] rx_packet;
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reg rx_burst;
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wire rx_lclk_iddr;
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wire [8:0] rxi_delay_in;
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wire [8:0] rxi_delay_out;
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reg reset_sync;
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//Reset sync
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always @ (posedge rx_lclk)
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reset_sync <= reset;
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//#####################
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//#CREATE 112 BIT PACKET
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//#####################
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//TODO: clean up!
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//write Pointer
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always @ (posedge rx_lclk)
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if (~rx_frame_sync[1]) begin
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rx_pointer <= 3'b0; //new frame
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access <= 1'b0;
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end
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else if (rx_pointer != 3'd6 && (rx_frame_sync != 2'b00))
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begin
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rx_pointer <= rx_pointer + 1; //anticipate burst
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access <= 1'b0;
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end
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else begin
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rx_pointer <= 3'd3;//middle of frame
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access <= 1'b1;
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end
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// shift register for rx_word
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always @ (posedge rx_lclk)
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case (rx_frame_sync[1:0])
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2'b01 : begin
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rx_sample[111:8] <= rx_sample[103:0];
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rx_sample[7:0] <= rx_word_sync[7:0];
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end
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2'b10 : begin
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rx_sample[111:8] <= rx_sample[103:0];
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rx_sample[7:0] <= rx_word_sync[15:8];
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end
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2'b11 : begin
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rx_sample[111:16] <= rx_sample[95:0];
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rx_sample[15:0] <= rx_word_sync[15:0];
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end
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default :
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rx_sample <= rx_sample;
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endcase // case (rx_frame_sync[1:0])
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//#####################
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//#DATA VALID SIGNAL
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//####################
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always @ (posedge rx_lclk)
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begin
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valid_packet <= access;//data pipeline
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end
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reg burst_detect;
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always @ (posedge rx_lclk)
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if(access & rx_frame_sync[1])
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burst_detect <= 1'b1;
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else if(~rx_frame_sync)
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burst_detect <= 1'b0;
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//###################################
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//#SAMPLE AND HOLD DATA
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//###################################
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//(..and shuffle data for 104 bit packet)
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always @ (posedge rx_lclk)
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if(access)
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begin
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//pipelin burst (delay by one frame)
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burst <= burst_detect;
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//access
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rx_packet_lclk[0] <= rx_sample[64];
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//write
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rx_packet_lclk[1] <= rx_sample[65];
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//datamode
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rx_packet_lclk[3:2] <= rx_sample[67:66];
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//ctrlmode
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rx_packet_lclk[7:4] <= rx_sample[103:100];
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//dstaddr
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rx_packet_lclk[39:8] <= rx_sample[99:68];
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//data
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rx_packet_lclk[71:40] <= rx_sample[63:32];
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//srcaddr
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rx_packet_lclk[103:72]<= rx_sample[31:0];
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end
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//###################################
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//#SYNCHRONIZE TO SLOW CLK
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//###################################
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//stretch access pulse to 4 cycles
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pulse_stretcher #(.DW(3))
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ps0 (
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.out(access_wide),
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.in(valid_packet),
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.clk(rx_lclk),
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.reset(reset_sync));
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always @ (posedge rx_lclk_div4)
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rx_access <= access_wide;
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always @ (posedge rx_lclk_div4)
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if(access_wide)
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begin
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rx_packet[PW-1:0] <= rx_packet_lclk[PW-1:0];
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rx_burst <= burst;
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end
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//################################
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//# I/O Buffers Instantiation
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//################################
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IBUFDS #(.DIFF_TERM ("TRUE"),.IOSTANDARD (IOSTD_ELINK))
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ibuf_data[7:0]
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(.I (rxi_data_p[7:0]),
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.IB (rxi_data_n[7:0]),
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.O (rxi_data[7:0]));
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IBUFDS #(.DIFF_TERM ("TRUE"), .IOSTANDARD (IOSTD_ELINK))
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ibuf_frame
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(.I (rxi_frame_p),
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.IB (rxi_frame_n),
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.O (rxi_frame));
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IBUFGDS #(.DIFF_TERM ("TRUE"),.IOSTANDARD (IOSTD_ELINK))
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ibuf_lclk (.I (rxi_lclk_p),
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.IB (rxi_lclk_n),
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.O (rxi_lclk)
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);
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`ifdef EPHYCARD
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OBUFT #(.IOSTANDARD("LVCMOS18"), .SLEW("SLOW"))
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obuft_wrwait (
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.O(rxo_wr_wait_p),
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.T(rx_wr_wait),
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.I(1'b0)
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);
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OBUFT #(.IOSTANDARD("LVCMOS18"), .SLEW("SLOW"))
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obuft_rdwait (
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.O(rxo_rd_wait_p),
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.T(rx_rd_wait),
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.I(1'b0)
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);
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`else
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OBUFDS #(.IOSTANDARD(IOSTD_ELINK),.SLEW("SLOW"))
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obufds_wrwait (
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.O(rxo_wr_wait_p),
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.OB(rxo_wr_wait_n),
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.I(rx_wr_wait)
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);
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OBUFDS #(.IOSTANDARD(IOSTD_ELINK),.SLEW("SLOW"))
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obufds_rdwait (.O(rxo_rd_wait_p),
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.OB(rxo_rd_wait_n),
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.I(rx_rd_wait)
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);
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`endif
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//###################################
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//#RX CLOCK
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//###################################
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BUFG rxi_lclk_bufg_i(.I(rxi_lclk), .O(rx_lclk_pll));
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BUFIO rx_lclk_bufio_i(.I(rxi_lclk), .O(rx_lclk_iddr));
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//###################################
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//#IDELAY CIRCUIT
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//###################################
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assign rxi_delay_in[8:0] ={rxi_frame,rxi_data[7:0]};
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genvar j;
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generate for(j=0; j<9; j=j+1)
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begin : gen_idelay
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(* IODELAY_GROUP = "IDELAY_GROUP" *) // Group name for IDELAYCTRL
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IDELAYE2 #(.CINVCTRL_SEL("FALSE"),
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.DELAY_SRC("IDATAIN"),
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.HIGH_PERFORMANCE_MODE("FALSE"),
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.IDELAY_TYPE("FIXED"),
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.IDELAY_VALUE(0), //(RX_TAP_DELAY[j]
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.PIPE_SEL("FALSE"),
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.REFCLK_FREQUENCY(200.0),
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.SIGNAL_PATTERN("DATA"))
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idelay_inst (.CNTVALUEOUT(),
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.DATAOUT(rxi_delay_out[j]),
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.C(1'b0),
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.CE(1'b0),
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.CINVCTRL(1'b0),
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.CNTVALUEIN(5'b0),
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.DATAIN(1'b0),
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.IDATAIN(rxi_delay_in[j]),
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.INC(1'b0),
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.LD(1'b0),
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.LDPIPEEN(1'b0),
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.REGRST(1'b0)
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);
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end // block: gen_idelay
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endgenerate
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//#############################
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//# IDDR SAMPLERS
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//#############################
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//DATA
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genvar i;
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generate for(i=0; i<8; i=i+1)
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begin : gen_iddr
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IDDR #(.DDR_CLK_EDGE ("SAME_EDGE"), .SRTYPE("ASYNC"))
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iddr_data (
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.Q1 (rx_word[i]),
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.Q2 (rx_word[i+8]),
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.C (rx_lclk_iddr),
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.CE (1'b1),
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.D (rxi_delay_out[i]),
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.R (reset_sync),
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.S (1'b0)
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);
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end
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endgenerate
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//FRAME
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IDDR #(.DDR_CLK_EDGE ("SAME_EDGE"), .SRTYPE("ASYNC"))
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iddr_frame (
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.Q1 (rx_frame[0]),
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.Q2 (rx_frame[1]),
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.C (rx_lclk_iddr),
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.CE (1'b1),
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.D (rxi_delay_out[8]),
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.R (reset_sync),
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.S (1'b0)
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);
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//Pipe stage
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always @ (posedge rx_lclk)
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rx_frame_sync <= rx_frame;
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//Pipe stage
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always @ (posedge rx_lclk)
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rx_word_sync <= rx_word;
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endmodule // erx_io
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// Local Variables:
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// verilog-library-directories:("." "../../emesh/hdl" "../../common/hdl")
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// End:
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/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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Contributed by Gunnar Hillerstrom
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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