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52 lines
1.4 KiB
Verilog
52 lines
1.4 KiB
Verilog
/*
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Copyright (C) 2013 Adapteva, Inc.
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Contributed by Andreas Olofsson <support@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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module mux3(/*AUTOARG*/
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// Outputs
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out,
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// Inputs
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in0, in1, in2, sel0, sel1, sel2
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);
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parameter DW=99;
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//data inputs
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input [DW-1:0] in0;
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input [DW-1:0] in1;
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input [DW-1:0] in2;
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//select inputs
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input sel0;
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input sel1;
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input sel2;
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output [DW-1:0] out;
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assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] |
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{(DW){sel1}} & in1[DW-1:0] |
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{(DW){sel2}} & in2[DW-1:0]);
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// synthesis translate_off
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always @*
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if((sel0+sel1+sel2>1) && ($time>0))
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$display("ERROR>>Arbitration failure in cell %m");
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// synthesis translate_on
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endmodule // mux3
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