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67 lines
2.7 KiB
Verilog
67 lines
2.7 KiB
Verilog
/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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Contributed by Fred Huettig <fred@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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module elink_tx(/*AUTOARG*/
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// Outputs
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txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p,
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txo_data_n, etx_rdfifo_access, etx_rdfifo_wait, etx_wrfifo_access,
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etx_wrfifo_wait, etx_wbfifo_access, etx_wbfifo_wait,
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// Inputs
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reset, clk, ecfg_coreid, txi_wr_wait_p, txi_wr_wait_n,
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txi_rd_wait_p, txi_rd_wait_n, ecfg_tx_enable, ecfg_tx_mmu_mode,
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ecfg_tx_gpio_mode, ecfg_tx_ctrl_mode, ecfg_tx_clkdiv,
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ecfg_tx_dataout
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);
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//Global signals
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input reset; //reset (hw+sw reset)
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input clk; //clock input for what?
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input [11:0] ecfg_coreid; //coordinate, used for srcaddr for example
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//IO side interface
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output txo_lclk_p; //high speed clock (up to 500MHz)
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output txo_lclk_n;
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output txo_frame_p; //frame signal to indicate start/stop
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output txo_frame_n;
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output [7:0] txo_data_p; //transmit data (dual data rate)
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output [7:0] txo_data_n;
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input txi_wr_wait_p; //incoming pushback on write transactions
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input txi_wr_wait_n;
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input txi_rd_wait_p; //incoming pushback on read transactions
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input txi_rd_wait_n;
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//control signals
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input ecfg_tx_enable; //enable signal for TX
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input ecfg_tx_mmu_mode; //enables MMU on transnmit path
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input ecfg_tx_gpio_mode; //forces TX outputs to constants
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input [3:0] ecfg_tx_ctrl_mode; //value for emesh ctrlmode tag
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input [3:0] ecfg_tx_clkdiv; //transmit clock divider
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input [8:0] ecfg_tx_dataout; //data for data[7:0] and frame in GPIO mode
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//Monitor output signals
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output etx_rdfifo_access; //read request from slave
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output etx_rdfifo_wait;
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output etx_wrfifo_access; //write request from slave
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output etx_wrfifo_wait;
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output etx_wbfifo_access; //writeback from master
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output etx_wbfifo_wait;
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endmodule // elink_tx
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