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247 lines
7.3 KiB
Verilog
247 lines
7.3 KiB
Verilog
/*
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File: ewrapper_io_tx_slow.v
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This file is part of the Parallella Project .
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Copyright (C) 2013 Adapteva, Inc.
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Contributed by Roman Trogan <support@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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module ewrapper_io_tx_slow
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(/*AUTOARG*/
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// Outputs
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DATA_OUT_TO_PINS_P, DATA_OUT_TO_PINS_N, LCLK_OUT_TO_PINS_P,
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LCLK_OUT_TO_PINS_N,
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// Inputs
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CLK_IN, CLK_IN_90, CLK_DIV_IN, CLK_RESET, IO_RESET, elink_disable,
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DATA_OUT_FROM_DEVICE
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);
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//###########
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//# INPUTS
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//###########
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input CLK_IN; // Fast clock input from PLL/MMCM
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input CLK_IN_90; // Fast clock input with 90deg phase shift
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input CLK_DIV_IN; // Slow clock input from PLL/MMCM
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input CLK_RESET;
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input IO_RESET;
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input elink_disable;
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input [71:0] DATA_OUT_FROM_DEVICE;
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//#############
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//# OUTPUTS
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//#############
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output [8:0] DATA_OUT_TO_PINS_P;
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output [8:0] DATA_OUT_TO_PINS_N;
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output LCLK_OUT_TO_PINS_P;
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output LCLK_OUT_TO_PINS_N;
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//############
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//# REGS
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//############
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reg [1:0] clk_cnt;
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reg tx_coreclock_del_45;
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reg tx_coreclock_del_135;
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reg [8:0] clk_even_reg;
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reg [8:0] clk_odd_reg;
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reg [71:0] tx_in_sync;
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reg tx_pedge_first;
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reg [3:0] cycle_sel;
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//############
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//# WIRES
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//############
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wire txo_lclk;
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wire txo_lclk90;
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wire tx_coreclock;
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wire reset;
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wire [8:0] clk_even;
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wire [8:0] clk0_even;
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wire [8:0] clk1_even;
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wire [8:0] clk2_even;
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wire [8:0] clk3_even;
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wire [8:0] clk_odd;
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wire [8:0] clk0_odd;
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wire [8:0] clk1_odd;
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wire [8:0] clk2_odd;
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wire [8:0] clk3_odd;
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wire [71:0] tx_in;
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wire [8:0] tx_out;
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wire tx_lclk_out;
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wire [8:0] DATA_OUT_TO_PINS_P;
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wire [8:0] DATA_OUT_TO_PINS_N;
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wire LCLK_OUT_TO_PINS_P;
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wire LCLK_OUT_TO_PINS_N;
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// Inversions for E16/E64 migration
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`ifdef TARGET_E16
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wire elink_invert = 1'b0;
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`elsif TARGET_E64
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wire elink_invert = 1'b1;
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`endif
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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assign reset = IO_RESET;
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assign tx_in[71:0] = DATA_OUT_FROM_DEVICE[71:0];
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assign txo_lclk = CLK_IN;
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assign txo_lclk90 = CLK_IN_90;
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assign tx_coreclock = CLK_DIV_IN;
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//#################################################
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//# Synchronize incoming data to fast clock domain
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//#################################################
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always @ (posedge txo_lclk)
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if(tx_pedge_first)
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tx_in_sync <= elink_invert ? ~tx_in : tx_in;
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//################################
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//# Output Buffers Instantiation
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//################################
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OBUFTDS #(.IOSTANDARD (`IOSTD_ELINK))
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obufds_inst [8:0]
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(.O (DATA_OUT_TO_PINS_P),
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.OB (DATA_OUT_TO_PINS_N),
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.I (tx_out),
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.T ({1'b0, {8{elink_disable}}})); // Frame is always enabled
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OBUFDS #(.IOSTANDARD (`IOSTD_ELINK))
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obufds_lclk_inst
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(.O (LCLK_OUT_TO_PINS_P),
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.OB (LCLK_OUT_TO_PINS_N),
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.I (tx_lclk_out));
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//#############################
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//# ODDR instantiation
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//#############################
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ODDR #(
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.DDR_CLK_EDGE ("SAME_EDGE"),
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.INIT (1'b0),
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.SRTYPE ("ASYNC"))
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oddr_inst [8:0]
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(
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.Q (tx_out),
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.C (txo_lclk),
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.CE (1'b1),
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.D1 (clk_even_reg),
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.D2 (clk_odd_reg),
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.R (reset),
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.S (1'b0));
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ODDR #(
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.DDR_CLK_EDGE ("SAME_EDGE"),
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.INIT (1'b0),
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.SRTYPE ("ASYNC"))
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oddr_lclk_inst
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(
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.Q (tx_lclk_out),
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.C (txo_lclk90),
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.CE (1'b1),
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.D1 (~elink_invert & ~elink_disable),
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.D2 (elink_invert & ~elink_disable),
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.R (CLK_RESET),
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.S (1'b0));
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//########################
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//# Data Serialization
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//########################
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always @ (posedge txo_lclk) begin
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clk_even_reg[8:0] <= clk_even[8:0];
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clk_odd_reg[8:0] <= clk_odd[8:0];
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end
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mux4 #(18) mux4
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(// Outputs
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.out ({clk_even[8:0],clk_odd[8:0]}),
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// Inputs
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.in0 ({clk0_even[8:0],clk0_odd[8:0]}),
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.sel0 (cycle_sel[0]),
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.in1 ({clk1_even[8:0],clk1_odd[8:0]}),
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.sel1 (cycle_sel[1]),
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.in2 ({clk2_even[8:0],clk2_odd[8:0]}),
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.sel2 (cycle_sel[2]),
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.in3 ({clk3_even[8:0],clk3_odd[8:0]}),
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.sel3 (cycle_sel[3]));
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//#################################
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//# Serialization Cycle Counter
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//#################################
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always @ (posedge txo_lclk) begin
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tx_pedge_first <= tx_coreclock_del_45 & tx_coreclock_del_135;
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cycle_sel[0] <= tx_pedge_first;
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cycle_sel[3:1] <= cycle_sel[2:0];
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end
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//################################################################
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//# Posedge Detection of the Slow Clock in the Fast Clock Domain
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//################################################################
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always @ (negedge txo_lclk) begin
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tx_coreclock_del_45 <= tx_coreclock;
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tx_coreclock_del_135 <= tx_coreclock_del_45;
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end
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//##################################
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//# Data Alignment Channel-to-Byte
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//##################################
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assign clk0_even[8:0] ={tx_in_sync[71],tx_in_sync[63],tx_in_sync[55],
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tx_in_sync[47],tx_in_sync[39],tx_in_sync[31],
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tx_in_sync[23],tx_in_sync[15],tx_in_sync[7]};
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assign clk0_odd[8:0] ={tx_in_sync[70],tx_in_sync[62],tx_in_sync[54],
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tx_in_sync[46],tx_in_sync[38],tx_in_sync[30],
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tx_in_sync[22],tx_in_sync[14],tx_in_sync[6]};
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assign clk1_even[8:0] ={tx_in_sync[69],tx_in_sync[61],tx_in_sync[53],
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tx_in_sync[45],tx_in_sync[37],tx_in_sync[29],
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tx_in_sync[21],tx_in_sync[13],tx_in_sync[5]};
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assign clk1_odd[8:0] ={tx_in_sync[68],tx_in_sync[60],tx_in_sync[52],
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tx_in_sync[44],tx_in_sync[36],tx_in_sync[28],
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tx_in_sync[20],tx_in_sync[12],tx_in_sync[4]};
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assign clk2_even[8:0] ={tx_in_sync[67],tx_in_sync[59],tx_in_sync[51],
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tx_in_sync[43],tx_in_sync[35],tx_in_sync[27],
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tx_in_sync[19],tx_in_sync[11],tx_in_sync[3]};
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assign clk2_odd[8:0] ={tx_in_sync[66],tx_in_sync[58],tx_in_sync[50],
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tx_in_sync[42],tx_in_sync[34],tx_in_sync[26],
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tx_in_sync[18],tx_in_sync[10],tx_in_sync[2]};
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assign clk3_even[8:0] ={tx_in_sync[65],tx_in_sync[57],tx_in_sync[49],
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tx_in_sync[41],tx_in_sync[33],tx_in_sync[25],
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tx_in_sync[17],tx_in_sync[9], tx_in_sync[1]};
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assign clk3_odd[8:0] ={tx_in_sync[64],tx_in_sync[56],tx_in_sync[48],
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tx_in_sync[40],tx_in_sync[32],tx_in_sync[24],
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tx_in_sync[16],tx_in_sync[8], tx_in_sync[0]};
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endmodule // ewrapper_io_tx_slow
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