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21 lines
701 B
Verilog
21 lines
701 B
Verilog
//#############################################################################
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//# Function: And-Or-Inverter (aoi33) Gate #
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//# Copyright: OH Project Authors. ALl rights Reserved. #
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//# License: MIT (see LICENSE file in OH repository) #
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//#############################################################################
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module oh_aoi33 #(parameter DW = 1 ) // array width
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(
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input [DW-1:0] a0,
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input [DW-1:0] a1,
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input [DW-1:0] a2,
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input [DW-1:0] b0,
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input [DW-1:0] b1,
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input [DW-1:0] b2,
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output [DW-1:0] z
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);
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assign z = ~((a0 & a1 & a2) | (b0 & b1 & b2));
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endmodule
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