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100 lines
2.7 KiB
Verilog
100 lines
2.7 KiB
Verilog
module dut(/*AUTOARG*/
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// Outputs
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dut_active, wait_out, access_out, packet_out,
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// Inputs
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clk, nreset, vdd, vss, access_in, packet_in, wait_in
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);
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parameter AW = 32;
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parameter DW = 32;
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parameter CW = 2;
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parameter IDW = 12;
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parameter M_IDW = 6;
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parameter S_IDW = 12;
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parameter PW = 104;
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parameter N = 1;
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//#######################################
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//# CLOCK AND RESET
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//#######################################
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input clk;
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input nreset;
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input [N*N-1:0] vdd;
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input vss;
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output dut_active;
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//#######################################
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//#EMESH INTERFACE
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//#######################################
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//Stimulus Driven Transaction
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input [N-1:0] access_in;
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input [N*PW-1:0] packet_in;
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output [N-1:0] wait_out;
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//DUT driven transactoin
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output [N-1:0] access_out;
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output [N*PW-1:0] packet_out;
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input [N-1:0] wait_in;
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [AW-1:0] gpio_en; // From gpio of gpio.v
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wire [AW-1:0] gpio_ilat; // From gpio of gpio.v
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wire gpio_irq; // From gpio of gpio.v
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wire [AW-1:0] gpio_out; // From gpio of gpio.v
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wire [31:0] reg_rdata; // From gpio of gpio.v
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// End of automatics
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wire [AW-1:0] gpio_in; // To gpio of gpio.v
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reg [N-1:0] access_out;
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//######################################################################
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//DUT
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//######################################################################
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assign gpio_in[AW-1:0] = 32'h87654321;
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assign wait_out[N-1:0] = 'b0;
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assign dut_active = 1'b1;
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always @ (posedge clk)
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access_out[0] <= access_in[0] & ~packet_in[0];
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emesh2packet e2p (// Outputs
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.packet_out (packet_out[PW-1:0]),
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// Inputs
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.write_out (1'b0),
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.datamode_out (2'b10),
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.ctrlmode_out (5'b0),
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.dstaddr_out ({(AW){1'b0}}),
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.data_out (reg_rdata[AW-1:0]),
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.srcaddr_out ({(AW){1'b0}})
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);
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/*gpio AUTO_TEMPLATE(.gpio_irq (gpio_irq),
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.gpio_\(.*\) (gpio_\1[AW-1:0]),
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);
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*/
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gpio #(.N(AW))
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gpio (.reg_access (access_in[0]),
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.reg_packet (packet_in[PW-1:0]),
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.gpio_in (gpio_in[AW-1:0]),
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/*AUTOINST*/
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// Outputs
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.reg_rdata (reg_rdata[31:0]),
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.gpio_out (gpio_out[AW-1:0]), // Templated
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.gpio_en (gpio_en[AW-1:0]), // Templated
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.gpio_irq (gpio_irq), // Templated
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.gpio_ilat (gpio_ilat[AW-1:0]), // Templated
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// Inputs
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.nreset (nreset),
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.clk (clk));
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endmodule // dut
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// Local Variables:
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// verilog-library-directories:("." "../hdl" "../../emesh/hdl")
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// End:
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