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oh/accelerator/fpga/run_params.tcl
2016-01-20 18:45:20 -05:00

20 lines
317 B
Tcl

#Design name ("system" recommended)
set design system
#Project directory ("." recommended)
set projdir ./
#Device name
set partname "xc7z020clg400-1"
#Paths to all IP blocks to use in Vivado "system.bd"
set ip_repos [list "."]
#All source files
set hdl_files []
#All constraints files
set constraints_files []