mirror of
https://github.com/aolofsson/oh.git
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438 lines
17 KiB
Verilog
438 lines
17 KiB
Verilog
`define CFG_FAKECLK 1 /*stupid verilator doesn't get clock gating*/
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`define CFG_MDW 32 /*Width of mesh network*/
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`define CFG_DW 32 /*Width of datapath*/
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`define CFG_AW 32 /*Width of address space*/
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`define CFG_LW 8 /*Link port width*/
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module dv_elink(/*AUTOARG*/
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// Outputs
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dut_passed, dut_failed, dut_rd_wait, dut_wr_wait, dut_access,
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dut_packet,
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// Inputs
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clk, reset, ext_access, ext_packet, ext_rd_wait, ext_wr_wait
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);
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parameter AW = 32;
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parameter DW = 32;
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parameter CW = 2; //number of clocks to send int
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parameter IDW = 12;
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parameter PW = 104;
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//Basic
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input [CW-1:0] clk; // Core clock
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input reset; // Reset
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output dut_passed; // Indicates passing test
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output dut_failed; // Indicates failing test
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//Input Transaction
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input ext_access;
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input [PW-1:0] ext_packet;
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output dut_rd_wait;
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output dut_wr_wait;
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//Output Transaction
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output dut_access;
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output [PW-1:0] dut_packet;
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input ext_rd_wait;
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input ext_wr_wait;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire elink0_cclk_n; // From elink0 of elink.v
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wire elink0_cclk_p; // From elink0 of elink.v
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wire elink0_chip_resetb; // From elink0 of elink.v
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wire [11:0] elink0_chipid; // From elink0 of elink.v
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wire elink0_mailbox_full; // From elink0 of elink.v
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wire elink0_mailbox_not_empty;// From elink0 of elink.v
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wire elink0_rx_lclk_div4; // From elink0 of elink.v
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wire elink0_rxo_rd_wait_n; // From elink0 of elink.v
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wire elink0_rxo_rd_wait_p; // From elink0 of elink.v
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wire elink0_rxo_wr_wait_n; // From elink0 of elink.v
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wire elink0_rxo_wr_wait_p; // From elink0 of elink.v
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wire elink0_rxrd_access; // From elink0 of elink.v
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wire [PW-1:0] elink0_rxrd_packet; // From elink0 of elink.v
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wire elink0_rxrr_access; // From elink0 of elink.v
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wire [PW-1:0] elink0_rxrr_packet; // From elink0 of elink.v
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wire elink0_rxwr_access; // From elink0 of elink.v
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wire [PW-1:0] elink0_rxwr_packet; // From elink0 of elink.v
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wire elink0_timeout; // From elink0 of elink.v
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wire elink0_tx_lclk_div4; // From elink0 of elink.v
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wire [7:0] elink0_txo_data_n; // From elink0 of elink.v
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wire [7:0] elink0_txo_data_p; // From elink0 of elink.v
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wire elink0_txo_frame_n; // From elink0 of elink.v
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wire elink0_txo_frame_p; // From elink0 of elink.v
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wire elink0_txo_lclk_n; // From elink0 of elink.v
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wire elink0_txo_lclk_p; // From elink0 of elink.v
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wire elink0_txrd_wait; // From elink0 of elink.v
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wire elink0_txrr_wait; // From elink0 of elink.v
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wire elink0_txwr_wait; // From elink0 of elink.v
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wire elink1_cclk_n; // From elink1 of elink.v
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wire elink1_cclk_p; // From elink1 of elink.v
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wire elink1_chip_resetb; // From elink1 of elink.v
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wire [11:0] elink1_chipid; // From elink1 of elink.v
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wire elink1_mailbox_full; // From elink1 of elink.v
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wire elink1_mailbox_not_empty;// From elink1 of elink.v
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wire elink1_rx_lclk_div4; // From elink1 of elink.v
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wire elink1_rxo_rd_wait_n; // From elink1 of elink.v
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wire elink1_rxo_rd_wait_p; // From elink1 of elink.v
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wire elink1_rxo_wr_wait_n; // From elink1 of elink.v
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wire elink1_rxo_wr_wait_p; // From elink1 of elink.v
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wire elink1_rxrd_access; // From elink1 of elink.v
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wire [PW-1:0] elink1_rxrd_packet; // From elink1 of elink.v
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wire elink1_rxrr_access; // From elink1 of elink.v
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wire [PW-1:0] elink1_rxrr_packet; // From elink1 of elink.v
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wire elink1_rxwr_access; // From elink1 of elink.v
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wire [PW-1:0] elink1_rxwr_packet; // From elink1 of elink.v
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wire elink1_timeout; // From elink1 of elink.v
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wire elink1_tx_lclk_div4; // From elink1 of elink.v
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wire [7:0] elink1_txo_data_n; // From elink1 of elink.v
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wire [7:0] elink1_txo_data_p; // From elink1 of elink.v
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wire elink1_txo_frame_n; // From elink1 of elink.v
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wire elink1_txo_frame_p; // From elink1 of elink.v
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wire elink1_txo_lclk_n; // From elink1 of elink.v
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wire elink1_txo_lclk_p; // From elink1 of elink.v
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wire elink1_txrd_wait; // From elink1 of elink.v
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wire elink1_txrr_access; // From emem of ememory.v
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wire [PW-1:0] elink1_txrr_packet; // From emem of ememory.v
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wire elink1_txrr_wait; // From elink1 of elink.v
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wire elink1_txwr_wait; // From elink1 of elink.v
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// End of automatics
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wire [3:0] colid;
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wire [3:0] rowid;
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wire mailbox_full;
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wire mailbox_not_empty;
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wire cclk_p, cclk_n;
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wire chip_resetb;
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wire emem_access;
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wire [PW-1:0] emem_packet;
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wire dut_access;
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wire [PW-1:0] dut_packet;
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wire rxrr_access;
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wire [PW-1:0] rxrr_packet;
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wire rxwr_access;
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wire [PW-1:0] rxwr_packet;
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wire rxrd_access;
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wire [PW-1:0] rxrd_packet;
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wire elink0_txrr_access;
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wire [PW-1:0] elink0_txrr_packet;
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wire elink0_txwr_access;
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wire [PW-1:0] elink0_txwr_packet;
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wire elink0_txrd_access;
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wire [PW-1:0] elink0_txrd_packet;
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wire elink1_txwr_access;
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wire [PW-1:0] elink1_txwr_packet;
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wire elink1_txrd_access;
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wire [PW-1:0] elink1_txrd_packet;
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wire emem_wait;
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reg [31:0] etime;
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wire itrace = 1'b1;
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//Clocks
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wire clkin = clk[0]; //for pll-->cclk, rxclk, txclk
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//Read path
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assign elink0_txrd_access = ext_access & ~ext_packet[1];
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assign elink0_txrd_packet[PW-1:0] = ext_packet[PW-1:0];
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//Write path
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assign elink0_txwr_access = ext_access & ext_packet[1];
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assign elink0_txwr_packet[PW-1:0] = ext_packet[PW-1:0];
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//TX Pushback
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assign dut_rd_wait = elink0_txrd_wait | elink2_wait_out;
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assign dut_wr_wait = elink0_txwr_wait | elink2_wait_out ;
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//Getting results back
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assign dut_access = elink0_rxrr_access;
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assign dut_packet[PW-1:0] = elink0_rxrr_packet[PW-1:0];
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//No pushback testing on elink0
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assign elink0_rxrd_wait = 1'b0;
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assign elink0_rxwr_wait = 1'b0;
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assign elink0_rxrr_wait = 1'b0;
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//not connected
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assign elink0_txrr_access = 1'b0;
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assign elink0_txrr_packet[PW-1:0] = 'b0;
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/*elink AUTO_TEMPLATE (.reset (reset),
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// Outputs
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.clkbypass ({clkin,clkin,clkin}),
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.clkin (clkin),
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.sys_clk (clk[1]),
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.\(.*\) (@"(substring vl-cell-name 0 6)"_\1[]),
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);
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*/
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defparam elink0.ID = 12'h810;
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elink elink0 (.testmode (1'b0),//tie to 1 to enable
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.rxi_lclk_p (elink1_txo_lclk_p),
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.rxi_lclk_n (elink1_txo_lclk_n),
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.rxi_frame_p (elink1_txo_frame_p),
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.rxi_frame_n (elink1_txo_frame_n),
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.rxi_data_p (elink1_txo_data_p[7:0]),
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.rxi_data_n (elink1_txo_data_n[7:0]),
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.txi_wr_wait_p (elink1_rxo_wr_wait_p),
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.txi_wr_wait_n (elink1_rxo_wr_wait_n),
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.txi_rd_wait_p (elink1_rxo_rd_wait_p),
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.txi_rd_wait_n (elink1_rxo_rd_wait_n),
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/*AUTOINST*/
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// Outputs
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.rx_lclk_div4 (elink0_rx_lclk_div4), // Templated
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.tx_lclk_div4 (elink0_tx_lclk_div4), // Templated
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.rxo_wr_wait_p (elink0_rxo_wr_wait_p), // Templated
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.rxo_wr_wait_n (elink0_rxo_wr_wait_n), // Templated
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.rxo_rd_wait_p (elink0_rxo_rd_wait_p), // Templated
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.rxo_rd_wait_n (elink0_rxo_rd_wait_n), // Templated
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.txo_lclk_p (elink0_txo_lclk_p), // Templated
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.txo_lclk_n (elink0_txo_lclk_n), // Templated
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.txo_frame_p (elink0_txo_frame_p), // Templated
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.txo_frame_n (elink0_txo_frame_n), // Templated
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.txo_data_p (elink0_txo_data_p[7:0]), // Templated
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.txo_data_n (elink0_txo_data_n[7:0]), // Templated
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.chipid (elink0_chipid[11:0]), // Templated
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.chip_resetb (elink0_chip_resetb), // Templated
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.cclk_p (elink0_cclk_p), // Templated
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.cclk_n (elink0_cclk_n), // Templated
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.rxwr_access (elink0_rxwr_access), // Templated
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.rxwr_packet (elink0_rxwr_packet[PW-1:0]), // Templated
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.rxrd_access (elink0_rxrd_access), // Templated
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.rxrd_packet (elink0_rxrd_packet[PW-1:0]), // Templated
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.rxrr_access (elink0_rxrr_access), // Templated
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.rxrr_packet (elink0_rxrr_packet[PW-1:0]), // Templated
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.txwr_wait (elink0_txwr_wait), // Templated
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.txrd_wait (elink0_txrd_wait), // Templated
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.txrr_wait (elink0_txrr_wait), // Templated
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.mailbox_not_empty (elink0_mailbox_not_empty), // Templated
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.mailbox_full (elink0_mailbox_full), // Templated
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.timeout (elink0_timeout), // Templated
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// Inputs
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.reset (reset), // Templated
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.clkin (clkin), // Templated
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.sys_clk (clk[1]), // Templated
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.clkbypass ({clkin,clkin,clkin}), // Templated
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.rxwr_wait (elink0_rxwr_wait), // Templated
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.rxrd_wait (elink0_rxrd_wait), // Templated
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.rxrr_wait (elink0_rxrr_wait), // Templated
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.txwr_access (elink0_txwr_access), // Templated
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.txwr_packet (elink0_txwr_packet[PW-1:0]), // Templated
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.txrd_access (elink0_txrd_access), // Templated
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.txrd_packet (elink0_txrd_packet[PW-1:0]), // Templated
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.txrr_access (elink0_txrr_access), // Templated
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.txrr_packet (elink0_txrr_packet[PW-1:0])); // Templated
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//No read/write from elink1 (for now)
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assign elink1_txrd_access = 1'b0;
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assign elink1_txrd_packet = 'b0;
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assign elink1_txwr_access = 1'b0;
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assign elink1_txwr_packet = 'b0;
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assign elink1_rxrr_wait = 1'b0;
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defparam elink1.ID = 12'h820;
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elink elink1 (.rxi_lclk_p (elink0_txo_lclk_p),
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.rxi_lclk_n (elink0_txo_lclk_n),
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.rxi_frame_p (elink0_txo_frame_p),
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.rxi_frame_n (elink0_txo_frame_n),
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.rxi_data_p (elink0_txo_data_p[7:0]),
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.rxi_data_n (elink0_txo_data_n[7:0]),
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.txi_wr_wait_p (elink0_rxo_wr_wait_p),
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.txi_wr_wait_n (elink0_rxo_wr_wait_n),
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.txi_rd_wait_p (elink0_rxo_rd_wait_p),
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.txi_rd_wait_n (elink0_rxo_rd_wait_n),
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/*AUTOINST*/
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// Outputs
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.rx_lclk_div4 (elink1_rx_lclk_div4), // Templated
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.tx_lclk_div4 (elink1_tx_lclk_div4), // Templated
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.rxo_wr_wait_p (elink1_rxo_wr_wait_p), // Templated
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.rxo_wr_wait_n (elink1_rxo_wr_wait_n), // Templated
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.rxo_rd_wait_p (elink1_rxo_rd_wait_p), // Templated
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.rxo_rd_wait_n (elink1_rxo_rd_wait_n), // Templated
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.txo_lclk_p (elink1_txo_lclk_p), // Templated
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.txo_lclk_n (elink1_txo_lclk_n), // Templated
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.txo_frame_p (elink1_txo_frame_p), // Templated
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.txo_frame_n (elink1_txo_frame_n), // Templated
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.txo_data_p (elink1_txo_data_p[7:0]), // Templated
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.txo_data_n (elink1_txo_data_n[7:0]), // Templated
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.chipid (elink1_chipid[11:0]), // Templated
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.chip_resetb (elink1_chip_resetb), // Templated
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.cclk_p (elink1_cclk_p), // Templated
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.cclk_n (elink1_cclk_n), // Templated
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.rxwr_access (elink1_rxwr_access), // Templated
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.rxwr_packet (elink1_rxwr_packet[PW-1:0]), // Templated
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.rxrd_access (elink1_rxrd_access), // Templated
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.rxrd_packet (elink1_rxrd_packet[PW-1:0]), // Templated
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.rxrr_access (elink1_rxrr_access), // Templated
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.rxrr_packet (elink1_rxrr_packet[PW-1:0]), // Templated
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.txwr_wait (elink1_txwr_wait), // Templated
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.txrd_wait (elink1_txrd_wait), // Templated
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.txrr_wait (elink1_txrr_wait), // Templated
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.mailbox_not_empty (elink1_mailbox_not_empty), // Templated
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.mailbox_full (elink1_mailbox_full), // Templated
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.timeout (elink1_timeout), // Templated
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// Inputs
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.reset (reset), // Templated
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.clkin (clkin), // Templated
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.sys_clk (clk[1]), // Templated
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.clkbypass ({clkin,clkin,clkin}), // Templated
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.testmode (elink1_testmode), // Templated
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.rxwr_wait (elink1_rxwr_wait), // Templated
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.rxrd_wait (elink1_rxrd_wait), // Templated
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.rxrr_wait (elink1_rxrr_wait), // Templated
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.txwr_access (elink1_txwr_access), // Templated
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.txwr_packet (elink1_txwr_packet[PW-1:0]), // Templated
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.txrd_access (elink1_txrd_access), // Templated
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.txrd_packet (elink1_txrd_packet[PW-1:0]), // Templated
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.txrr_access (elink1_txrr_access), // Templated
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.txrr_packet (elink1_txrr_packet[PW-1:0])); // Templated
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elink_e16 elink2 (
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// Outputs
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.rxi_rd_wait (),
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.rxi_wr_wait (),
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.txo_data (),
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.txo_lclk (),
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.txo_frame (),
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.c0_mesh_access_out(),
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.c0_mesh_write_out (),
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.c0_mesh_dstaddr_out(),
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.c0_mesh_srcaddr_out(),
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.c0_mesh_data_out (),
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.c0_mesh_datamode_out(),
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.c0_mesh_ctrlmode_out(),
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.c0_emesh_wait_out (),
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.c0_mesh_wait_out (elink2_wait_out),
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// Inputs
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.reset (reset),
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.c0_clk_in (clk[1]),
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.c1_clk_in (clk[1]),
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.c2_clk_in (clk[1]),
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.c3_clk_in (clk[1]),
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.rxi_data (elink0_txo_data_p[7:0]),
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.rxi_lclk (elink0_txo_lclk_p),
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.rxi_frame (elink0_txo_frame_p),
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.txo_rd_wait (1'b0),
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.txo_wr_wait (1'b0),
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.c0_mesh_access_in (ext_access),
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.c0_mesh_write_in (ext_packet[1]),
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.c0_mesh_dstaddr_in(ext_packet[39:8]),
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.c0_mesh_srcaddr_in(ext_packet[103:72]),
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.c0_mesh_data_in (ext_packet[71:40]),
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.c0_mesh_datamode_in(ext_packet[3:2]),
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.c0_mesh_ctrlmode_in(ext_packet[7:4])
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);
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assign emem_access = (elink1_rxwr_access & ~(elink1_rxwr_packet[39:28]==elink1.ID)) |
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(elink1_rxrd_access & ~(elink1_rxrd_packet[39:28]==elink1.ID));
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assign emem_packet[PW-1:0] = elink1_rxwr_access ? elink1_rxwr_packet[PW-1:0]:
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elink1_rxrd_packet[PW-1:0];
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assign elink1_rxrd_wait = emem_wait | elink1_rxwr_access;
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assign elink1_rxwr_wait = 1'b0; //no wait on write
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/*ememory AUTO_TEMPLATE (
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// Outputs
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.\(.*\)_out (elink1_txrr_\1[]),
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.\(.*\)_in (emem_\1[]),
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.wait_out (emem_wait),
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);
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*/
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ememory emem (.wait_in (1'b0), //only one read at a time, set to zero for no1
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.clk (clk[1]),
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|
.wait_out (emem_wait),
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|
/*AUTOINST*/
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|
// Outputs
|
|
.access_out (elink1_txrr_access), // Templated
|
|
.packet_out (elink1_txrr_packet[PW-1:0]), // Templated
|
|
// Inputs
|
|
.reset (reset),
|
|
.access_in (emem_access), // Templated
|
|
.packet_in (emem_packet[PW-1:0])); // Templated
|
|
|
|
//Transaction Monitor
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|
|
|
always @ (posedge clkin or posedge reset)
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|
if(reset)
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|
etime[31:0] <= 32'b0;
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|
else
|
|
etime[31:0] <= etime[31:0]+1'b1;
|
|
|
|
/*emesh_monitor AUTO_TEMPLATE (
|
|
// Outputs
|
|
.emesh_\(.*\) (@"(substring vl-cell-name 0 3)"_\1[]),
|
|
);
|
|
*/
|
|
|
|
|
|
emesh_monitor #(.NAME("stimulus")) ext_monitor (.emesh_wait ((dut_rd_wait | dut_wr_wait)),//TODO:fix collisions
|
|
.clk (clk[1]),
|
|
/*AUTOINST*/
|
|
// Inputs
|
|
.reset (reset),
|
|
.itrace (itrace),
|
|
.etime (etime[31:0]),
|
|
.emesh_access (ext_access), // Templated
|
|
.emesh_packet (ext_packet[PW-1:0])); // Templated
|
|
|
|
emesh_monitor #(.NAME("dut")) dut_monitor (.emesh_wait (1'b0),
|
|
.clk (clk[1]),
|
|
/*AUTOINST*/
|
|
// Inputs
|
|
.reset (reset),
|
|
.itrace (itrace),
|
|
.etime (etime[31:0]),
|
|
.emesh_access (dut_access), // Templated
|
|
.emesh_packet (dut_packet[PW-1:0])); // Templated
|
|
|
|
emesh_monitor #(.NAME("emem")) mem_monitor (.emesh_wait (1'b0),
|
|
.clk (clk[1]),
|
|
.emesh_access (emem_access),
|
|
.emesh_packet (emem_packet[PW-1:0]),
|
|
/*AUTOINST*/
|
|
// Inputs
|
|
.reset (reset),
|
|
.itrace (itrace),
|
|
.etime (etime[31:0]));
|
|
|
|
|
|
endmodule // dv_elink
|
|
// Local Variables:
|
|
// verilog-library-directories:("." "../hdl" "../../memory/hdl")
|
|
// End:
|
|
|
|
/*
|
|
Copyright (C) 2014 Adapteva, Inc.
|
|
Contributed by Andreas Olofsson <andreas@adapteva.com>
|
|
|
|
This program is free software: you can redistribute it and/or modify
|
|
it under the terms of the GNU General Public License as published by
|
|
the Free Software Foundation, either version 3 of the License, or
|
|
(at your option) any later version.This program is distributed in the hope
|
|
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
|
|
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
GNU General Public License for more details. You should have received a copy
|
|
of the GNU General Public License along with this program (see the file
|
|
COPYING). If not, see <http://www.gnu.org/licenses/>.
|
|
*/
|
|
|