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87 lines
3.1 KiB
Verilog
87 lines
3.1 KiB
Verilog
/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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module axi_slave_memif (/*AUTOARG*/
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// Outputs
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s_axi_awready, s_axi_wready, s_axi_bresp, s_axi_bvalid,
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s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, mi_addr,
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mi_access, mi_write, mi_data_in,
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// Inputs
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s_axi_aclk, s_axi_aresetn, s_axi_awaddr, s_axi_awprot,
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s_axi_awvalid, s_axi_wdata, s_axi_wstrb, s_axi_wvalid,
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s_axi_bready, s_axi_araddr, s_axi_arprot, s_axi_arvalid,
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s_axi_rready, mi_readback_data
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);
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parameter AW = 32; //axi addr width
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parameter DW = 32; //axi data width
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parameter SW = DW/8;//==ADW/8
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/*****************************/
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/*AXI SLAVE INTERFACE */
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/*****************************/
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//Global signals
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input s_axi_aclk; //clock source for axi slave interfaces
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input s_axi_aresetn; //synchronous reset signal, active low
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//Write address channel
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input [AW-1:0] s_axi_awaddr; //write address
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input [2:0] s_axi_awprot; //protection type
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input s_axi_awvalid; //write address valid
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output s_axi_awready; //write address ready
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//Write data channel
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input [DW-1:0] s_axi_wdata; //write data
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input [SW-1:0] s_axi_wstrb; //write strobes
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input s_axi_wvalid; //write valid
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output s_axi_wready; //write channel ready
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//Buffered write response channel
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input s_axi_bready; //write ready
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output [1:0] s_axi_bresp; //write response
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output s_axi_bvalid; //write response valid
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//Read address channel
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input [AW-1:0] s_axi_araddr; //read address
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input [2:0] s_axi_arprot; //protection type
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input s_axi_arvalid; //read address valid
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output s_axi_arready; //read address ready
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//Read data channel
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output [DW-1:0] s_axi_rdata; //read data
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output [1:0] s_axi_rresp; //read response
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output s_axi_rvalid; //read valid
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input s_axi_rready; //read ready
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/*****************************/
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/*MEORY INTERFACE */
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/*****************************/
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output [19:0] mi_addr;
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output mi_access;
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output mi_write;
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output [DW-1:0] mi_data_in;
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input [DW-1:0] mi_readback_data;
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//Dummy interface, need to instantiate IP!!!
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//this will lock up AXI bus
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`ifdef CFG_XILINX
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`endif
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endmodule // axi_memif
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