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103 lines
4.1 KiB
Verilog
103 lines
4.1 KiB
Verilog
//########################
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//AXI MASTER INTERFACE
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//########################
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module aximaster_stub (/*AUTOARG*/
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// Outputs
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m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize, m_axi_awburst,
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m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awqos,
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m_axi_awvalid, m_axi_wid, m_axi_wdata, m_axi_wstrb, m_axi_wlast,
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m_axi_wvalid, m_axi_bready, m_axi_arid, m_axi_araddr, m_axi_arlen,
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m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache,
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m_axi_arprot, m_axi_arqos, m_axi_arvalid, m_axi_rready,
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// Inputs
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m_axi_aclk, m_axi_aresetn, m_axi_awready, m_axi_wready, m_axi_bid,
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m_axi_bresp, m_axi_bvalid, m_axi_arready, m_axi_rid, m_axi_rdata,
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m_axi_rresp, m_axi_rlast, m_axi_rvalid
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);
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parameter M_IDW = 12;
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//reset+clock
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input m_axi_aclk; // global clock signal.
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input m_axi_aresetn; // global reset singal.
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//Write address channel
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output [M_IDW-1:0] m_axi_awid; // write address ID
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output [31 : 0] m_axi_awaddr; // master interface write address
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output [7 : 0] m_axi_awlen; // burst length.
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output [2 : 0] m_axi_awsize; // burst size.
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output [1 : 0] m_axi_awburst; // burst type.
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output m_axi_awlock; // lock type
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output [3 : 0] m_axi_awcache; // memory type.
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output [2 : 0] m_axi_awprot; // protection type.
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output [3 : 0] m_axi_awqos; // quality of service
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output m_axi_awvalid; // write address valid
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input m_axi_awready; // write address ready
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//Write data channel
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output [M_IDW-1:0] m_axi_wid;
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output [63 : 0] m_axi_wdata; // master interface write data.
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output [7 : 0] m_axi_wstrb; // byte write strobes
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output m_axi_wlast; // indicates last transfer in a write burst.
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output m_axi_wvalid; // indicates data is ready to go
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input m_axi_wready; // indicates that the slave is ready for data
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//Write response channel
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input [M_IDW-1:0] m_axi_bid;
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input [1 : 0] m_axi_bresp; // status of the write transaction.
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input m_axi_bvalid; // channel is signaling a valid write response
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output m_axi_bready; // master can accept write response.
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//Read address channel
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output [M_IDW-1:0] m_axi_arid; // read address ID
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output [31 : 0] m_axi_araddr; // initial address of a read burst
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output [7 : 0] m_axi_arlen; // burst length
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output [2 : 0] m_axi_arsize; // burst size
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output [1 : 0] m_axi_arburst; // burst type
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output m_axi_arlock; //lock type
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output [3 : 0] m_axi_arcache; // memory type
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output [2 : 0] m_axi_arprot; // protection type
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output [3 : 0] m_axi_arqos; //
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output m_axi_arvalid; // valid read address and control information
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input m_axi_arready; // slave is ready to accept an address
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//Read data channel
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input [M_IDW-1:0] m_axi_rid;
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input [63 : 0] m_axi_rdata; // master read data
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input [1 : 0] m_axi_rresp; // status of the read transfer
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input m_axi_rlast; // signals last transfer in a read burst
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input m_axi_rvalid; // signaling the required read data
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output m_axi_rready; // master can accept the readback data
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//tieoffs
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assign m_axi_awid ='b0;
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assign m_axi_awaddr ='b0;
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assign m_axi_awlen ='b0;
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assign m_axi_awsize ='b0;
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assign m_axi_awburst ='b0;
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assign m_axi_awlock ='b0;
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assign m_axi_awcache ='b0;
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assign m_axi_awprot ='b0;
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assign m_axi_awqos ='b0;
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assign m_axi_awvalid ='b0;
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assign m_axi_wid ='b0;
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assign m_axi_wdata ='b0;
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assign m_axi_wstrb ='b0;
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assign m_axi_wlast ='b0;
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assign m_axi_wvalid ='b0;
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assign m_axi_bready ='b0;
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assign m_axi_arid ='b0;
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assign m_axi_araddr ='b0;
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assign m_axi_arlen ='b0;
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assign m_axi_arsize ='b0;
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assign m_axi_arburst ='b0;
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assign m_axi_arlock ='b0;
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assign m_axi_arcache ='b0;
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assign m_axi_arprot ='b0;
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assign m_axi_arqos ='b0;
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assign m_axi_arvalid ='b0;
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assign m_axi_rready ='b0;
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endmodule // maxi_stub
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