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159 lines
5.1 KiB
Markdown
159 lines
5.1 KiB
Markdown
Mini-IO: A lightweight IO interface
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=============================================
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1. [Features](#features)
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2. [Registers](#registers)
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3. [Interface](#interface)
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4. [Parameters](#parameters)
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5. [Code](#code)
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6. [Driver](#driver)
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7. [Authors](#authors)
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8. [License](#license)
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## Introduction
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* Mini-IO (MIO) is a generic protocol agnostic link for moving data between chips (or silicon dies).
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## Features
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* Source synchronous
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* Clock aligned by transmitter at 90 degrees
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* Parametrized I/O and system side bus width
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* Configurable as single or dual data rate
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* Configurable as lsb or msb first transfer
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## Registers
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| Register Name |Addr[5:2]| Access | Default | Description |
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|---------------|---------|--------|---------|--------------------------------|
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| MIO_CONFIG | 0x0 | RD/WR | L | Configuration register |
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| MIO_STATUS | 0x1 | RD/WR | n/a | Status register |
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| MIO_CLKDIV | 0x2 | RD/WR | H | TX frequency setting |
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| MIO_CLKPHASE | 0x3 | RD/WR | n/a | TX phase setting |
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| MIO_ODELAY | 0x5 | RD/WR | n/a | TX output data delay |
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| MIO_IDELAY | 0x4 | RD/WR | n/a | RX input data delay |
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| MIO_ADDR0 | 0x6 | RD/WR | n/a | Lower 32 bits of auto-address |
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| MIO_ADDR1 | 0x7 | RD/WR | n/a | Upper 32 bits of auto-address |
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**MIO_CONFIG:**
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| FIELD | DESCRIPTION |
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|-------- |-------------------------------------|
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| [0] | TX disable |
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| [1] | RX disable |
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| [3:2] | Transfer mode |
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| | 00=Emesh packet mode "emode" |
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| | 01=Data streaming mode "dmode" |
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| | 10=Auto address mode "amode" |
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| [11:4] | Number of flits/packet |
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| | For emode:
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| | 0=1 (byte) |
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| | 0=2 (16 bit) |
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| | 0=4 (32 bit) |
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| | 0=8 (64 bit) |
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| [12] | DDR mode |
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| [13] | Transfer MSB first |
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| [18:14] | Emesh ctrlmode |
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**MIO_STATUS:**
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| FIELD | DESCRIPTION |
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|-------- |-------------------------------------|
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| [0] | RX fifo empty |
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| [1] | RX programmable full reached |
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| [2] | RX full reached |
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| [3] | TX fifo empty |
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| [4] | TX programmable full reached |
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| [5] | TX full reached |
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| [7:6] | Reserved |
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| [15:8] | Sticky versions fo bit [7:0] |
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**MIO_CLKDIV:**
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| FIELD | DESCRIPTION |
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|-------- |-------------------------------------|
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| [7:0] | Clock period setting |
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| | 0:clkout=clkin |
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| | 1:clkout=clkin/2 |
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| | 2:clkout=clkin/3 |
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| | 3:clkout=clkin/4 |
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| | etc... |
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**MIO_CLKPHASE:**
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| FIELD | DESCRIPTION |
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|-------- |-------------------------------------|
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| [7:0] | TX IO clock rising edge |
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| [15:8] | TX IO clock falling edge |
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| [23:16] | TX transmit clock rising edge |
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| [31:24] | TX transmit clock rising edge |
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**MIO_ODELAY:**
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* TBD
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**MIO_IDELAY:**
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* TBD
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**MIO_ADDR0:**
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| FIELD | DESCRIPTION |
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|-------- |-------------------------------------|
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| [31:0] | Lower 32 bits of address in amode |
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**MIO_ADDR1:**
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| FIELD | DESCRIPTION |
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|-------- |-------------------------------------|
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| [31:0] | Upper 32 bits of address in amode |
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## Interface
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| SIGNAL | DIR| DESCRIPTION
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| -------------------|----|--------------
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| access_in | I | Valid packet for TX
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| data_in | I | Data for TX
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| wait_out | O | Pushback from TX towards core side
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| access_out | I | Valid packet from RX
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| data_out | I | Data from RX
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| wait_in | O | Pushback for RX from core side
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| tx_access | O | TX packet framing signal
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| tx_clk | O | TX clock aligned in the center of the data eye
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| tx_data | I | TX DDR data
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| tx_wait | I | TX pushback from RX
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| rx_access | I | RX packet framing signal
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| rx_clk | I | RX center aligned clock
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| rx_data | I | RX DDR data
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| rx_wait | O | RX pushback for TX
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| clk | I | Core side clock
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| nreset | I | Active low async reset
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| io_clk | I | Clock for transmit side
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| datasize[7:0] | I | Size of data to transmit (<PW)
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| divcfg[7:0] | I | Divider setting for TX clock divider
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## Parameters
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* N : IO data width
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* PW: core side packet width
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## Code
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* [mio.v](hdl/mio.v)
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* [mio_regs.v](hdl/mio_regs.v)
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## Authors
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* Andreas Olofsson
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## License
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* MIT
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