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138 lines
4.3 KiB
Verilog
138 lines
4.3 KiB
Verilog
`include "mio_regmap.vh"
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module mio_if (/*AUTOARG*/
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// Outputs
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access_out, packet_out, rx_wait_out,
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// Inputs
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clk, nreset, amode, emode, lsbfirst, ctrlmode, dstaddr, wait_in,
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rx_access_in, rx_packet_in
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);
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//#####################################################################
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//# INTERFACE
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//#####################################################################
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//parameters
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parameter AW = 32; // address width
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parameter PW = 104; // emesh packet width
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parameter MPW = 128; // mio packet width (> PW)
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// reset, clk, config
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input clk; // main core clock
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input nreset; // async active low reset
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input emode; // emesh mode
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input [4:0] ctrlmode; // emode ctrlmode
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input amode; // auto address mode
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input [AW-1:0] dstaddr; // amode destination address
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input [1:0] datamode; // amode datamode
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//
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// core interface
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output access_out; // pass through
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output [PW-1:0] packet_out; // packet for core from rx
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input wait_in; // pass through
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// datapath interface (fifo)
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input rx_access_in; // pass through
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input [MPW-1:0] rx_packet_in; // packet from rx fifo
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output rx_wait_out; // pass through
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//#####################################################################
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//# BODY
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//#####################################################################
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wire [4:0] ctrlmode_out;
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wire [AW-1:0] data_out;
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wire [1:0] datamode_out;
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wire [AW-1:0] dstaddr_out;
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wire [AW-1:0] srcaddr_out;
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wire write_out;
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wire [1:0] datamode;
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wire [3:0] addr_stride;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [4:0] ctrlmode_in; // From pe2 of packet2emesh.v
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wire [AW-1:0] data_in; // From pe2 of packet2emesh.v
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wire [1:0] datamode_in; // From pe2 of packet2emesh.v
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wire [AW-1:0] dstaddr_in; // From pe2 of packet2emesh.v
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wire [AW-1:0] srcaddr_in; // From pe2 of packet2emesh.v
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wire write_in; // From pe2 of packet2emesh.v
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// End of automatics
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/*AUTOINPUT*/
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wire [3:0] datasize;
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//#################################################
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// TRANSACTION FOR CORE (FROM RX)
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//#################################################
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// parse packet
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packet2emesh #(.AW(AW),
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.PW(PW))
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pe2 (.packet_in (rx_packet_in[PW-1:0]),
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/*AUTOINST*/
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// Outputs
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.write_in (write_in),
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.datamode_in (datamode_in[1:0]),
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.ctrlmode_in (ctrlmode_in[4:0]),
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.dstaddr_in (dstaddr_in[AW-1:0]),
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.srcaddr_in (srcaddr_in[AW-1:0]),
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.data_in (data_in[AW-1:0]));
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// datamode
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assign datamode[1:0] = (datasize[3:0]==4'd1) ? 2'b00 :
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(datasize[3:0]==4'd2) ? 2'b01 :
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(datasize[3:0]==4'd4) ? 2'b10 :
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2'b11;
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//#################################################
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// TRANSACTION FOR CORE (FROM RX)
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//#################################################
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// write only for amode (streaming data)
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assign write_out = amode ? 1'b1 :
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write_in;
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// translate datasize to datamode
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assign datamode_out[1:0] = amode ? datamode[1:0] :
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datamode_in[1:0];
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// ctrlmode from register in amode
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assign ctrlmode_out[4:0] = amode ? ctrlmode[4:0] :
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ctrlmode_in[4:0];
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// address from
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assign dstaddr_out[AW-1:0] = amode ? dstaddr[AW-1:0] :
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dstaddr_in[AW-1:0];
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// data in first 64 bits for amode
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assign data_out[AW-1:0] = amode ? rx_packet_in[31:0] :
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data_in[AW-1:0];
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assign srcaddr_out[AW-1:0] = amode ? rx_packet_in[63:32] :
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srcaddr_in[AW-1:0];
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//Construct outgoing packet
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emesh2packet #(.AW(AW),
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.PW(PW))
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e2p (/*AUTOINST*/
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// Outputs
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.packet_out (packet_out[PW-1:0]),
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// Inputs
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.write_out (write_out),
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.datamode_out (datamode_out[1:0]),
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.ctrlmode_out (ctrlmode_out[4:0]),
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.dstaddr_out (dstaddr_out[AW-1:0]),
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.data_out (data_out[AW-1:0]),
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.srcaddr_out (srcaddr_out[AW-1:0]));
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endmodule // mio_if
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// Local Variables:
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// verilog-library-directories:("." "../../emesh/hdl")
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// End:
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