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17 lines
518 B
Systemverilog
17 lines
518 B
Systemverilog
`ifndef MIO_REGMAP_VH_
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`define MIO_REGMAP_VH_
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//Registers addr[5:2]
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`define MIO_CONFIG 4'd0 // general config
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`define MIO_STATUS 4'd1 // status
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`define MIO_CLKDIV 4'd2 // clk divider config
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`define MIO_CLKPHASE 4'd3 // clk divider config
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`define MIO_ODELAY 4'd4 // output data delay element
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`define MIO_IDELAY 4'd5 // input data delay element
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`define MIO_ADDR0 4'd6 // destination address for amode
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`define MIO_ADDR1 4'd7 // destination address for amode
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`endif // `ifndef MIO_REGMAP_VH_
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