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100 lines
3.4 KiB
Verilog
100 lines
3.4 KiB
Verilog
//#############################################################################
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//# Purpose: MIO Receive Datapath #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module mrx # ( parameter PW = 104, // fifo width
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parameter AW = 32, // fifo width
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parameter IOW = 8, // I./O data width
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parameter FIFO_DEPTH = 16, // fifo depth
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parameter TARGET = "GENERIC" // fifo target
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)
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(//reset, clk, cfg
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input clk, // main core clock
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input nreset, // async active low reset
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input ddr_mode,
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input [1:0] iowidth,
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input amode, // To mrx_fifo of mrx_fifo.v
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input [4:0] ctrlmode, // To mrx_fifo of mrx_fifo.v
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input [1:0] datamode, // To mrx_fifo of mrx_fifo.v
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input [AW-1:0] dstaddr, // To mrx_fifo of mrx_fifo.v
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input emode, // To mrx_fifo of mrx_fifo.v
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//status
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output rx_empty, // rx fifo is empty
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output rx_full, // rx fifo is full (should never happen!)
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output rx_prog_full,// rx is getting full (stop sending!)
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//IO interface
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input rx_clk, // clock from IO
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input rx_access, // access signal for IO
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input [IOW-1:0] rx_packet, // packet from IO
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output rx_wait, // pushback for IO
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// data
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output access_out, // fifo data valid
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output [PW-1:0] packet_out, // fifo packet
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input wait_in // wait pushback for fifo
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);
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/*AUTOOUTPUT*/
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire io_access; // From mrx_io of mrx_io.v
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wire [63:0] io_packet; // From mrx_io of mrx_io.v
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wire [7:0] io_valid; // From mrx_io of mrx_io.v
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// End of automatics
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//########################################
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//# Synchronization FIFO
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//########################################
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mrx_fifo #(.PW(PW),
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.AW(AW),
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.FIFO_DEPTH(FIFO_DEPTH),
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.TARGET(TARGET))
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mrx_fifo (/*AUTOINST*/
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// Outputs
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.rx_wait (rx_wait),
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.access_out (access_out),
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.packet_out (packet_out[PW-1:0]),
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// Inputs
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.clk (clk),
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.nreset (nreset),
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.emode (emode),
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.ctrlmode (ctrlmode[4:0]),
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.amode (amode),
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.dstaddr (dstaddr[AW-1:0]),
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.datamode (datamode[1:0]),
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.io_access (io_access),
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.io_valid (io_valid[7:0]),
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.io_packet (io_packet[63:0]),
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.rx_clk (rx_clk),
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.wait_in (wait_in));
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//########################################
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//# FAST IO (DDR)
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//########################################
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mrx_io #(.IOW(IOW))
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mrx_io (
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/*AUTOINST*/
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// Outputs
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.io_access (io_access),
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.io_valid (io_valid[7:0]),
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.io_packet (io_packet[63:0]),
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// Inputs
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.nreset (nreset),
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.ddr_mode (ddr_mode),
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.iowidth (iowidth[1:0]),
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.rx_clk (rx_clk),
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.rx_packet (rx_packet[IOW-1:0]),
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.rx_access (rx_access));
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endmodule // ctx
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// Local Variables:
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// verilog-library-directories:("." "../../common/hdl" "../../../oh/emesh/hdl")
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// End:
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