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15 lines
539 B
Systemverilog
15 lines
539 B
Systemverilog
//Registers addr[6:2], 64 bits per register
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`ifndef EDMA_REGMAP_VH_
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`define EDMA_REGMAP_VH_
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`define EDMA_CONFIG 5'd0 // general config
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`define EDMA_STRIDE 5'd1 // stride
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`define EDMA_COUNT 5'd2 // count
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`define EDMA_SRCADDR 5'd3 // source address
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`define EDMA_DSTADDR 5'd4 // destination address
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`define EDMA_SRCADDR64 5'd5 // extended source address (64b)
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`define EDMA_DSTADDR64 5'd6 // extended destinationa ddress (64b)
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`define EDMA_STATUS 5'd7 // status register
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`endif // `ifndef EDMA_REGMAP_VH_
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