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131 lines
4.0 KiB
Verilog
131 lines
4.0 KiB
Verilog
/*
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########################################################################
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ELINK CONFIGURATION REGISTER FILE
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########################################################################
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*/
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module ecfg_rx (/*AUTOARG*/
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// Outputs
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mi_dout, ecfg_rx_enable, ecfg_rx_mmu_enable,
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// Inputs
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reset, mi_clk, mi_en, mi_we, mi_addr, mi_din, ecfg_rx_datain,
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ecfg_rx_debug
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);
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/******************************/
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/*Compile Time Parameters */
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/******************************/
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parameter RFAW = 5; // 32 registers for now
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/******************************/
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/*HARDWARE RESET (EXTERNAL) */
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/******************************/
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input reset; // ecfg registers reset only by "hard reset"
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/*****************************/
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/*SIMPLE MEMORY INTERFACE */
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/*****************************/
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input mi_clk;
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input mi_en;
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input mi_we; // single we, must write 32 bit words
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input [19:0] mi_addr; // complete physical address (no shifting!)
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input [31:0] mi_din;
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output [31:0] mi_dout;
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/*****************************/
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/*CONFIG SIGNALS */
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/*****************************/
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//rx
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output ecfg_rx_enable; // enable signal for rx
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output ecfg_rx_mmu_enable; // enables MMU on rx path
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input [8:0] ecfg_rx_datain; // frame and data inputs
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input [15:0] ecfg_rx_debug; // erx debug signals
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/*------------------------CODE BODY---------------------------------------*/
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//registers
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reg [4:0] ecfg_rx_reg;
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reg [8:0] ecfg_datain_reg;
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reg [8:0] ecfg_datain_sync;
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reg [2:0] ecfg_rx_debug_reg;
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reg [31:0] mi_dout;
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//wires
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wire ecfg_read;
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wire ecfg_write;
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wire ecfg_rx_write;
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/*****************************/
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/*ADDRESS DECODE LOGIC */
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/*****************************/
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//read/write decode
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assign ecfg_write = mi_en & mi_we;
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assign ecfg_read = mi_en & ~mi_we;
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//Config write enables
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assign ecfg_rx_write = ecfg_write & (mi_addr[RFAW+1:2]==`ELRX);
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//###########################
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//# RXCFG
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//###########################
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always @ (posedge mi_clk)
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if(reset)
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ecfg_rx_reg[4:0] <= 5'b0;
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else if (ecfg_rx_write)
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ecfg_rx_reg[4:0] <= mi_din[4:0];
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assign ecfg_rx_enable = ecfg_rx_reg[0];
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assign ecfg_rx_mmu_enable = ecfg_rx_reg[1];
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//###########################
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//# DATAIN (synchronized)
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//###########################
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always @ (posedge mi_clk)
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begin
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ecfg_datain_sync[8:0] <= ecfg_rx_datain[8:0];
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ecfg_datain_reg[8:0] <= ecfg_datain_sync[8:0];
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end
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//###########################1
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//# DEBUG
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//###########################
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always @ (posedge mi_clk)
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if(reset)
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ecfg_rx_debug_reg[2:0] <= 'd0;
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else
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ecfg_rx_debug_reg[2:0] <=ecfg_rx_debug_reg[2:0] | ecfg_rx_debug[2:0];
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//###############################
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//# DATA READBACK MUX
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//###############################
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//Pipelineing readback
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always @ (posedge mi_clk)
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if(ecfg_read)
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case(mi_addr[RFAW+1:2])
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`ELRX: mi_dout[31:0] <= {27'b0, ecfg_rx_reg[4:0]};
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`ELDATAIN: mi_dout[31:0] <= {23'b0, ecfg_datain_reg[8:0]};
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default: mi_dout[31:0] <= 32'd0;
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endcase
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endmodule // ecfg
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/*
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Copyright (C) 2013 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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