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31 lines
749 B
Verilog
31 lines
749 B
Verilog
module oh_bin2gray (/*AUTOARG*/
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// Outputs
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gray,
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// Inputs
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bin
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);
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//###############################################################
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//# Interface
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//###############################################################
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input [DW-1:0] bin; //binary encoded input
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output [DW-1:0] gray; //gray encoded output
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parameter DW = 64; //width of converter
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//###############################################################
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//# BODY
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//###############################################################
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reg [DW-1:0] gray;
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integer i;
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always @*
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begin
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gray[DW-1] = bin[DW-1];
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for (i=0; i<(DW-1); i=i+1)
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gray[i] = bin[i] ^ bin[i+1];
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end
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endmodule // oh_bin2gray
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