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5bd5d1ff54
-added register read/write properly -removed redundant wrapper layers in maxi/saxi -changed over to "emesh" interface from packet 103 bit data -cleaned up maxi -cleaned up saxi -removed redundant signals in elink interface (user,lock,..) -added wrapper to fifo (to carry emesh interface through) Now comes the fun part of testing
18 lines
296 B
Batchfile
18 lines
296 B
Batchfile
../hdl/elink.v
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../../constants/hdl/xilinx_constants.v
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../../elink/hdl/elink_regmap.v
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-y .
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-y ../../elink/hdl
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-y ../../stubs/hdl
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-y ../../common/hdl
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-y ../../axi/hdl
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-y ../../memory/hdl
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-y ../../embox/hdl
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-y ../../emmu/hdl
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-y ../../ecfg/hdl
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-y ../../erx/hdl
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-y ../../etx/hdl
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-y ../../eclock/hdl
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