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33 lines
461 B
Verilog
33 lines
461 B
Verilog
module RAM32X1D (/*AUTOARG*/
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// Outputs
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DPO, SPO,
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// Inputs
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A0, A1, A2, A3, A4, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, WCLK, WE
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);
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//inputs
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input A0;
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input A1;
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input A2;
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input A3;
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input A4;
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input D;
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input DPRA0;
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input DPRA1;
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input DPRA2;
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input DPRA3;
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input DPRA4;
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input WCLK;
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input WE;
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//outputs
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output DPO;
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output SPO;
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assign DPO=1'b0;
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assign SPO=1'b0;
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endmodule // RAM32X1D
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