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51 lines
1.5 KiB
Verilog
51 lines
1.5 KiB
Verilog
//#############################################################################
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//# Function: Generic counter #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_counter #(parameter DW = 32 // width of data inputs
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)
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(
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//inputs
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input clk, // clk input
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input in, // input to count
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input en, // enable counter
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input dir,//0=increment, 1=decrement
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input autowrap, //auto wrap around
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input load, // load counter
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input [DW-1:0] load_data, // input data to load
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//outputs
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output [DW-1:0] count, // count value
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output wraparound // wraparound indicator
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);
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// local variables
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reg [DW-1:0] count;
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wire [DW-1:0] count_in;
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//Select count direction
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assign count_in[DW-1:0] = dir ? count[DW-1:0] - in :
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count[DW-1:0] + in ;
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// counter
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always @(posedge clk)
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if(load)
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count[DW-1:0] <= load_data[DW-1:0];
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else if (en & ~(wraparound & ~autowrap))
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count[DW-1:0] <= count_in[DW-1:0];
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// counter expired
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assign wraparound = (dir & en & ~(|count[DW-1:0])) |
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(~dir & en & (&count[DW-1:0]));
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endmodule // oh_counter
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