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de63dfd907
-stdcells moved to asiclib, doesn't make sense to be vectorized -common is a stupid name, renamed as stdlib
110 lines
3.1 KiB
Verilog
110 lines
3.1 KiB
Verilog
module emesh_readback (/*AUTOARG*/
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// Outputs
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ready_out, access_out, packet_out,
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// Inputs
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nreset, clk, access_in, packet_in, read_data, ready_in
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);
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parameter AW = 32; // address width
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parameter PW = 104; // packet width
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//clk, reset
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input nreset; // asynchronous active low reset
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input clk; // clock
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// input transaction
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input access_in; // register access
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input [PW-1:0] packet_in; // data/address
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output ready_out; // pushback from mesh
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// register/memory data (already pipelined)
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input [63:0] read_data; // data from register/memorye
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// output transaction
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output access_out; // register access
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output [PW-1:0] packet_out; // data/address
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input ready_in; // pushback from mesh
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [12:0] ctrlmode_in; // From p2e of packet2emesh.v
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wire [AW-1:0] data_in; // From p2e of packet2emesh.v
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wire [1:0] datamode_in; // From p2e of packet2emesh.v
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wire [AW-1:0] dstaddr_in; // From p2e of packet2emesh.v
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wire [AW-1:0] srcaddr_in; // From p2e of packet2emesh.v
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wire write_in; // From p2e of packet2emesh.v
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// End of automatics
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reg [1:0] datamode_out;
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reg [4:0] ctrlmode_out;
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reg [AW-1:0] dstaddr_out;
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wire [AW-1:0] data_out;
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wire [AW-1:0] srcaddr_out;
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reg access_out;
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//########################################
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//# Parse packet
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//#######################################
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enoc_unpack #(.AW(AW),
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.PW(PW))
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p2e (/*AUTOINST*/
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// Outputs
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.write_in (write_in),
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.datamode_in (datamode_in[1:0]),
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.ctrlmode_in (ctrlmode_in[12:0]),
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.dstaddr_in (dstaddr_in[AW-1:0]),
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.srcaddr_in (srcaddr_in[AW-1:0]),
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.data_in (data_in[AW-1:0]),
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// Inputs
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.packet_in (packet_in[PW-1:0]));
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//########################################
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//# Pipeline
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//#######################################
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//access
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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access_out <= 1'b0;
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else if(ready_in)
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access_out <= access_in & ~write_in;
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//packet
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always @ (posedge clk)
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if(ready_in & access_in & ~write_in)
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begin
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datamode_out[1:0] <= datamode_in[1:0];
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ctrlmode_out[4:0] <= ctrlmode_in[4:0];
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dstaddr_out[AW-1:0] <= srcaddr_in[AW-1:0];
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end
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assign data_out[AW-1:0] = read_data[31:0];
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assign srcaddr_out[AW-1:0] = read_data[63:32];
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//ready signal
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assign ready_out = ready_in;
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//########################################
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//# Convert to Packet
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//#######################################
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enoc_pack #(.AW(AW),
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.PW(PW))
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e2p (.write_out (1'b1),
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/*AUTOINST*/
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// Outputs
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.packet_out (packet_out[PW-1:0]),
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// Inputs
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.datamode_out (datamode_out[1:0]),
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.ctrlmode_out (ctrlmode_out[12:0]),
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.dstaddr_out (dstaddr_out[AW-1:0]),
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.data_out (data_out[AW-1:0]),
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.srcaddr_out (srcaddr_out[AW-1:0]));
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endmodule // emesh_readback
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// Local Variables:
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// verilog-library-directories:("." "../../emesh/hdl" "../../common/hdl")
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// End:
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