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38 lines
819 B
Verilog
38 lines
819 B
Verilog
module dut(/*AUTOARG*/
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// Outputs
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dut_active, clkout, wait_out, access_out, packet_out,
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// Inputs
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clk1, clk2, nreset, vdd, vss, access_in, packet_in, wait_in
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);
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//parameters
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parameter N = 1;
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parameter PW = 104;
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//clock, reset
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input clk1;
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input clk2;
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input nreset;
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input [N*N-1:0] vdd;
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input vss;
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output dut_active;
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output clkout;
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//Stimulus Driven Transaction
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input [N-1:0] access_in;
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input [N*PW-1:0] packet_in;
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output [N-1:0] wait_out;
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//DUT driven transactoin
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output [N-1:0] access_out;
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output [N*PW-1:0] packet_out;
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input [N-1:0] wait_in;
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assign dut_active = 1'b1;
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assign clkout = clkin1;
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assign clk = clkin1;
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endmodule // dut
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