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27 lines
624 B
Verilog
27 lines
624 B
Verilog
module oh_simchecker #(parameter DW = 32 // Datapath width
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)
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(
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//Inputs
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input clk,
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input nreset,
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input [DW-1:0] result, // result to check
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input [DW-1:0] reference, // reference result
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output reg diff //fail indicator
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);
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always @ (negedge clk or negedge nreset)
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if(~nreset)
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diff <= 1'b0;
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else if(result!==reference)
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begin
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diff <= 1'b1;
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`ifdef CFG_SIM
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$display("ERROR(%0t): result= %d(%h) reference= %d(%h)", $time, result,result, reference, reference);
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`endif
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end
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else
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diff <= 1'b0;
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endmodule // oh_simchecker
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