mirror of
https://github.com/aolofsson/oh.git
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110 lines
3.3 KiB
Tcl
110 lines
3.3 KiB
Tcl
###########################################################
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# IPI
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###########################################################
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create_project -force project_ipi ./project_ipi -part xc7z020clg400-1
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set_property target_language Verilog [current_project]
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###########################################################
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# Create Report/Results Directory
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###########################################################
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set report_dir ./reports
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set results_dir ./results
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if ![file exists $report_dir] {file mkdir $report_dir}
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if ![file exists $results_dir] {file mkdir $results_dir}
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###########################################################
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# Add Interfaces to IP Repository
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###########################################################
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set interfaces_repo_dir ../interfaces_repository
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set ip_repo_paths [get_property ip_repo_paths [current_project]]
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set_property ip_repo_paths "$interfaces_repo_dir $ip_repo_paths" [current_project]
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update_ip_catalog
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###########################################################
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# Add HLS IPs to IP Repository
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###########################################################
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set hls_ip_repo_dir ../hls_ip_repository
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set ip_repo_paths [get_property ip_repo_paths [current_project]]
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set_property ip_repo_paths "$hls_ip_repo_dir $ip_repo_paths" [current_project]
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update_ip_catalog
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###########################################################
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# Add eLink IP to IP Repository
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###########################################################
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set elink_ip_repo_dir ../elink_ip_repository
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set ip_repo_paths [get_property ip_repo_paths [current_project]]
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set_property ip_repo_paths "$elink_ip_repo_dir $ip_repo_paths" [current_project]
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update_ip_catalog
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###########################################################
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# Add ADI IPs to IP Repository
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###########################################################
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set adi_ip_repo_dir ../adi_ip_repository
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set ip_repo_paths [get_property ip_repo_paths [current_project]]
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set_property ip_repo_paths "$adi_ip_repo_dir $ip_repo_paths" [current_project]
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update_ip_catalog
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###########################################################
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# Create Block Design
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###########################################################
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create_bd_design "parallella_bd"
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source ./scripts/parallella_elink_base_bd.tcl
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validate_bd_design
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###########################################################
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# Write BD TCL
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###########################################################
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write_bd_tcl -force ${results_dir}/parallella_elink_base_bd.tcl
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###########################################################
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# Create HDL Wrapper
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###########################################################
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make_wrapper -files [get_files C:/Parallella/ipi_parallella_elink_base/project_ipi/project_ipi.srcs/sources_1/bd/parallella_bd/parallella_bd.bd] -top
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##
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add_files -norecurse C:/Parallella/ipi_parallella_elink_base/project_ipi/project_ipi.srcs/sources_1/bd/parallella_bd/hdl/parallella_bd_wrapper.v
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add_files -fileset constrs_1 -norecurse C:/Parallella/ipi_parallella_elink_base/sources/parallella_io.xdc
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add_files -fileset constrs_1 -norecurse C:/Parallella/ipi_parallella_elink_base/sources/parallella_timing.xdc
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###########################################################
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# Implement Design
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###########################################################
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launch_runs synth_1
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wait_on_run synth_1
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launch_runs impl_1
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wait_on_run impl_1
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