Andreas Olofsson 2e6130fd19 Adding valid signal to fifo ...

-Since data has one pipeline delay, this makes it much easier to use
-Matches better with Xilinx fifo generator

2015-04-27 11:15:06 -04:00

..

fifo_async_emesh.v

Added profull HACK to async_fifo

2015-04-17 15:49:58 -04:00

fifo_async.v

Adding valid signal to fifo

2015-04-27 11:15:06 -04:00

fifo_empty_block.v

Fixing startup issues in transmit path:

2015-04-15 16:33:20 -04:00

fifo_full_block.v

Fixed stupid typos on full/empty

2015-04-23 18:56:49 -04:00

fifo_mem.v

Continued work to create clean design:

2015-04-15 11:54:43 -04:00

fifo_sync.v

Made reset async (there may not be a clock..)

2015-04-24 17:32:17 -04:00

memory_dp.v

Adding platform agnostic dual ported memory and async fifo

2015-04-14 23:56:00 -04:00

memory_sp.v

Wrong port direction on output

2015-04-21 17:10:22 -04:00