1
0
mirror of https://github.com/aolofsson/oh.git synced 2025-01-30 02:32:53 +08:00
oh/xilibs/hdl/BUFIO.v
Andreas Olofsson 617214cc90 Cleanup
2015-04-22 13:56:29 -04:00

14 lines
133 B
Verilog

module BUFIO (/*AUTOARG*/
// Outputs
O,
// Inputs
I
);
output O;
input I;
assign O=I;
endmodule