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624d0e6134
-renamed disty for consistency (there is an arbiter there now) -adding missing ID to etx/erx -New org working!
200 lines
7.2 KiB
Verilog
200 lines
7.2 KiB
Verilog
module erx (/*AUTOARG*/
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// Outputs
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rx_lclk_div4, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p,
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rxo_rd_wait_n, rxwr_access, rxwr_packet, rxrd_access, rxrd_packet,
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rxrr_access, rxrr_packet, erx_cfg_wait, timeout, mailbox_full,
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mailbox_not_empty,
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// Inputs
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reset, sys_clk, rxi_lclk_p, rxi_lclk_n, rxi_frame_p, rxi_frame_n,
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rxi_data_p, rxi_data_n, rxwr_wait, rxrd_wait, rxrr_wait,
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erx_cfg_access, erx_cfg_packet
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);
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parameter AW = 32;
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parameter DW = 32;
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parameter PW = 104;
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parameter RFAW = 6;
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parameter ID = 12'h800;
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//reset & clock
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input reset;
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input sys_clk; //system input clock for fifos
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output rx_lclk_div4; //for synchronization outside erx
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//FROM IO Pins
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input rxi_lclk_p, rxi_lclk_n; //link rx clock input
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input rxi_frame_p, rxi_frame_n; //link rx frame signal
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input [7:0] rxi_data_p, rxi_data_n; //link rx data
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output rxo_wr_wait_p,rxo_wr_wait_n; //link rx write pushback output
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output rxo_rd_wait_p,rxo_rd_wait_n; //link rx read pushback output
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//Master write
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output rxwr_access;
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output [PW-1:0] rxwr_packet;
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input rxwr_wait;
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//Master read request
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output rxrd_access;
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output [PW-1:0] rxrd_packet;
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input rxrd_wait;
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//Slave read response
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output rxrr_access;
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output [PW-1:0] rxrr_packet;
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input rxrr_wait;
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//Configuration Interface (from ETX)
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input erx_cfg_access;
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input [PW-1:0] erx_cfg_packet;
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output erx_cfg_wait;
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//Readback timeout (synchronized to sys_c
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output timeout;
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output mailbox_full;
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output mailbox_not_empty;
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/*AUTOOUTPUT*/
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [63:0] rx_data_par; // From erx_io of erx_io.v
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wire [7:0] rx_frame_par; // From erx_io of erx_io.v
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wire rx_rd_wait; // From erx_core of erx_core.v
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wire rx_wr_wait; // From erx_core of erx_core.v
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wire rxrd_fifo_access; // From erx_core of erx_core.v
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wire [PW-1:0] rxrd_fifo_packet; // From erx_core of erx_core.v
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wire rxrd_fifo_wait; // From erx_fifo of erx_fifo.v
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wire rxrr_fifo_access; // From erx_core of erx_core.v
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wire [PW-1:0] rxrr_fifo_packet; // From erx_core of erx_core.v
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wire rxrr_fifo_wait; // From erx_fifo of erx_fifo.v
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wire rxwr_fifo_access; // From erx_core of erx_core.v
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wire [PW-1:0] rxwr_fifo_packet; // From erx_core of erx_core.v
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wire rxwr_fifo_wait; // From erx_fifo of erx_fifo.v
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// End of automatics
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//regs
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wire [15:0] rx_status;
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wire rxwr_fifo_full;
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wire rxrr_fifo_full;
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wire rxrd_fifo_full;
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wire rxrd_empty;
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wire rxwr_empty;
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wire rxrr_empty;
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wire [103:0] edma_packet; // From edma of edma.v, ...
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/***********************************************************/
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/*RECEIVER I/O LOGIC */
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/***********************************************************/
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erx_io erx_io (
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/*AUTOINST*/
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// Outputs
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.rxo_wr_wait_p (rxo_wr_wait_p),
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.rxo_wr_wait_n (rxo_wr_wait_n),
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.rxo_rd_wait_p (rxo_rd_wait_p),
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.rxo_rd_wait_n (rxo_rd_wait_n),
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.rx_lclk_div4 (rx_lclk_div4),
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.rx_frame_par (rx_frame_par[7:0]),
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.rx_data_par (rx_data_par[63:0]),
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// Inputs
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.reset (reset),
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.rxi_lclk_p (rxi_lclk_p),
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.rxi_lclk_n (rxi_lclk_n),
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.rxi_frame_p (rxi_frame_p),
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.rxi_frame_n (rxi_frame_n),
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.rxi_data_p (rxi_data_p[7:0]),
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.rxi_data_n (rxi_data_n[7:0]),
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.rx_wr_wait (rx_wr_wait),
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.rx_rd_wait (rx_rd_wait));
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/**************************************************************/
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/*ELINK CORE LOGIC */
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/**************************************************************/
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/*erx_core AUTO_TEMPLATE (
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.erx_cfg_access (erx_cfg_access),
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.erx_cfg_packet (erx_cfg_packet[PW-1:0]),
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.erx_cfg_wait (erx_cfg_wait),
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.rx_rd_wait (rx_rd_wait),
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.rx_wr_wait (rx_wr_wait),
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.\(.*\)_packet (\1_fifo_packet[PW-1:0]),
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.\(.*\)_access (\1_fifo_access),
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.\(.*\)_wait (\1_fifo_wait),
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);
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*/
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defparam erx_core.ID=ID;
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erx_core erx_core ( .clk (rx_lclk_div4),
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/*AUTOINST*/
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// Outputs
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.rx_rd_wait (rx_rd_wait), // Templated
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.rx_wr_wait (rx_wr_wait), // Templated
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.rxrd_access (rxrd_fifo_access), // Templated
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.rxrd_packet (rxrd_fifo_packet[PW-1:0]), // Templated
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.rxrr_access (rxrr_fifo_access), // Templated
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.rxrr_packet (rxrr_fifo_packet[PW-1:0]), // Templated
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.rxwr_access (rxwr_fifo_access), // Templated
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.rxwr_packet (rxwr_fifo_packet[PW-1:0]), // Templated
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.erx_cfg_wait (erx_cfg_wait), // Templated
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.mailbox_full (mailbox_full),
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.mailbox_not_empty(mailbox_not_empty),
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// Inputs
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.reset (reset),
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.rx_data_par (rx_data_par[63:0]),
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.rx_frame_par (rx_frame_par[7:0]),
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.rxrd_wait (rxrd_fifo_wait), // Templated
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.rxrr_wait (rxrr_fifo_wait), // Templated
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.rxwr_wait (rxwr_fifo_wait), // Templated
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.erx_cfg_access (erx_cfg_access), // Templated
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.erx_cfg_packet (erx_cfg_packet[PW-1:0])); // Templated
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/************************************************************/
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/*FIFOs */
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/************************************************************/
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erx_fifo erx_fifo (
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/*AUTOINST*/
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// Outputs
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.rxwr_access (rxwr_access),
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.rxwr_packet (rxwr_packet[PW-1:0]),
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.rxrd_access (rxrd_access),
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.rxrd_packet (rxrd_packet[PW-1:0]),
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.rxrr_access (rxrr_access),
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.rxrr_packet (rxrr_packet[PW-1:0]),
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.rxrd_fifo_wait (rxrd_fifo_wait),
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.rxrr_fifo_wait (rxrr_fifo_wait),
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.rxwr_fifo_wait (rxwr_fifo_wait),
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// Inputs
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.reset (reset),
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.rx_lclk_div4 (rx_lclk_div4),
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.sys_clk (sys_clk),
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.rxwr_wait (rxwr_wait),
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.rxrd_wait (rxrd_wait),
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.rxrr_wait (rxrr_wait),
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.rxrd_fifo_access(rxrd_fifo_access),
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.rxrd_fifo_packet(rxrd_fifo_packet[PW-1:0]),
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.rxrr_fifo_access(rxrr_fifo_access),
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.rxrr_fifo_packet(rxrr_fifo_packet[PW-1:0]),
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.rxwr_fifo_access(rxwr_fifo_access),
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.rxwr_fifo_packet(rxwr_fifo_packet[PW-1:0]));
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endmodule // erx
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// Local Variables:
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// verilog-library-directories:("." "../../emmu/hdl" "../../edma/hdl" "../../memory/hdl" "../../emailbox/hdl")
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// End:
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/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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