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d7d959da45
- This is DEFINITELY the way to do things, sweep the delays and find the right value. No f'ing way to get these stupid FPGAs to work otherwise with the ridiculuosly over margined PVT nubmers they are running through the STAs. I understand they want to make the design bullet proof, but as a result designers are wasting countless hours overoptimzinng designs and being clever. So much performance is left on the table for expert users. - Lesson: I/O design should be "self syncrhonizing". Only contraints in the design should be create_clk - Made RX clock async, too tricky to guarantee that there clock is there. No way to do this if the clock sources are actually independent for RX/TX!
49 lines
1.6 KiB
Verilog
49 lines
1.6 KiB
Verilog
`ifndef ELINK_REGMAP_V_
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`define ELINK_REGMAP_V_
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//MEMORY MAP
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//[31:20] = LINKID
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//[19:16] = GROUP SELECT
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//[15] = MMU SELECT (for RX/TX)
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//[14:11] = USED BY MMU ONLY
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//[10:8] = register group
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//[7:2] = REGISTER ADDRESS (0..63)
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//[1:0] = IGNORED (no byte access)
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//Link register groups addr[19:16]
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`define EGROUP_MMR 4'hF // reserved for registers
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`define EGROUP_MMU 4'hE // RX & TX MMU
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`define EGROUP_RR 4'hD // read response block
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//ETX-REGS
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`define E_RESET 6'd0 //F0200-reset
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`define E_CLK 6'd1 //F0204-clock configuration
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`define E_CHIPID 6'd2 //F0208-Epiphany chip id for colid/rowid pins
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`define E_VERSION 6'd3 //F020C-version #
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`define ETX_CFG 6'd4 //F0210-config
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`define ETX_STATUS 6'd5 //F0214-tx status
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`define ETX_GPIO 6'd6 //F0218-direct data for tx pins
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//ERX-REGS
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`define ERX_CFG 6'd0 //F0300-config
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`define ERX_STATUS 6'd1 //F0304-status register
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`define ERX_GPIO 6'd2 //F0308-sampled data
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`define ERX_OFFSET 6'd3 //F030C-memory base for remap
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`define E_MAILBOXLO 6'd4 //F0314-reserved-->move?
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`define E_MAILBOXHI 6'd5 //F0318-reserved
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`define ERX_IDELAY0 6'd6 //F0320-tap delay for d[3:0]
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`define ERX_IDELAY1 6'd7 //F0324-tap delays for {frame,d[7:4]}
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//DMA (same numbering as in Epiphany, limit to 4 channels)
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`define DMACFG 5'd0 //F0500/F0520
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`define DMACOUNT 5'd1 //F0504/F0524
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`define DMASTRIDE 5'd2 //F0508/F0528
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`define DMASRCADDR 5'd3 //F050C/F052c
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`define DMADSTADDR 5'd4 //F0510/F0530
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`define DMAAUTO0 5'd5 //F0514/F0534
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`define DMAAUTO1 5'd6 //F0518/F0538
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`define DMASTATUS 5'd7 //F051C/F053c
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`endif
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