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88 lines
2.1 KiB
Verilog
88 lines
2.1 KiB
Verilog
module fifo_async
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(/*AUTOARG*/
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// Outputs
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full, prog_full, dout, empty, valid,
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// Inputs
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wr_rst, rd_rst, wr_clk, rd_clk, wr_en, din, rd_en
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);
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parameter DW = 104; //FIFO width
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parameter DEPTH = 32; //FIFO depth
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parameter TYPE = "XILINX";//"BASIC" or "XILINX" or "ALTERA"
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//##########
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//# RESET/CLOCK
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//##########
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input wr_rst; //write reset
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input rd_rst; //read reset
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input wr_clk; //write clock
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input rd_clk; //read clock
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//##########
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//# FIFO WRITE
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//##########
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input wr_en;
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input [DW-1:0] din;
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output full;
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output prog_full;
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//###########
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//# FIFO READ
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//###########
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input rd_en;
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output [DW-1:0] dout;
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output empty;
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output valid;
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generate
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if(TYPE=="BASIC") begin : basic
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fifo_async_model
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#(.DEPTH(DEPTH),
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.DW(DW))
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fifo_model (.full (),
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.prog_full (prog_full),
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.almost_full (full),
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/*AUTOINST*/
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// Outputs
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.dout (dout[DW-1:0]),
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.empty (empty),
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.valid (valid),
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// Inputs
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.wr_rst (wr_rst),
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.rd_rst (rd_rst),
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.wr_clk (wr_clk),
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.rd_clk (rd_clk),
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.wr_en (wr_en),
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.din (din[DW-1:0]),
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.rd_en (rd_en));
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end
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else if (TYPE=="XILINX") begin : xilinx
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if((DW==104) & (DEPTH==32))
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begin
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fifo_async_104x32 fifo_async_104x32 (.full (),
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.prog_full (prog_full),
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.almost_full (full),
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/*AUTOINST*/
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// Outputs
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.dout (dout[DW-1:0]),
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.empty (empty),
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.valid (valid),
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// Inputs
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.wr_rst (wr_rst),
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.rd_rst (rd_rst),
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.wr_clk (wr_clk),
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.rd_clk (rd_clk),
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.wr_en (wr_en),
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.din (din[DW-1:0]),
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.rd_en (rd_en));
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end // if ((DW==104) & (DEPTH==32))
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end // block: xilinx
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endgenerate
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endmodule // fifo_async
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// Local Variables:
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// verilog-library-directories:("." "../fpga/" "../dv")
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// End:
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