Andreas Olofsson 36b0f14ca5 "Fixing" wait signal ...

- Giving a wait on every ack just doesn't make sense on the read port with a fifo there??
- Makes for a nasty combinatorial loop during integration.
- Test passes (but need to look into this more)

2015-11-03 19:49:38 -05:00

..

axi_elink.v

Adding active signal to interface

2015-11-03 19:49:09 -05:00

ecfg_elink.v

Link cleanup

2015-11-02 16:10:05 -05:00

ecfg_if.v

Link cleanup

2015-11-02 16:10:05 -05:00

eclocks.v

Link cleanup

2015-11-02 16:10:05 -05:00

elink_constants.v

Link cleanup

2015-11-02 16:10:05 -05:00

elink_regmap.v

Changing idelay bit map

2015-11-03 10:31:06 -05:00

elink.v

Link cleanup

2015-11-02 16:10:05 -05:00

emaxi.v

"Fixing" wait signal

2015-11-03 19:49:38 -05:00

ereset.v

Adding software programmable IDELAY

2015-10-07 11:49:46 -04:00

erx_arbiter.v

Shifting first byte of packet down by one bit to accomodate new format

2015-11-02 20:51:35 -05:00

erx_cfg.v

Changing idelay bit map

2015-11-03 10:31:06 -05:00

erx_clocks.v

Optimizing clock path

2015-11-03 14:15:09 -05:00

erx_core.v

Fixing pushback bug in emmu

2015-10-19 11:08:28 -04:00

erx_fifo.v

Copyright cleanup

2015-08-07 09:19:37 -04:00

erx_io.v

Optimizing clock path

2015-11-03 14:15:09 -05:00

erx_protocol.v

Shifting first byte of packet down by one bit to accomodate new format

2015-11-02 20:51:35 -05:00

erx_remap.v

Reset timing optimization

2015-10-08 10:34:59 -04:00

erx_timer.v

Converting to synchronous reset

2015-05-17 23:00:53 -04:00

erx.v

Link cleanup

2015-11-02 16:10:05 -05:00

esaxi.v

"Fixing" wait signal

2015-11-03 19:49:38 -05:00

etx_arbiter.v

Shifting first byte of packet down by one bit to accomodate new format

2015-11-02 20:51:35 -05:00

etx_cfg.v

Reset timing optimization

2015-10-08 10:34:59 -04:00

etx_clocks.v

Optimizing clock path

2015-11-03 14:15:09 -05:00

etx_core.v

Fixing pushback bug in emmu

2015-10-19 11:08:28 -04:00

etx_fifo.v

Fifo parameter change

2015-07-02 16:55:42 -04:00

etx_io.v

Optimizing clock path

2015-11-03 14:15:09 -05:00

etx_protocol.v

Link cleanup

2015-11-02 16:10:05 -05:00

etx_remap.v

Separate rd/wr stalls

2015-05-04 17:09:50 -04:00

etx.v

Optimizing clock path

2015-11-03 14:15:09 -05:00