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62 lines
1.2 KiB
Verilog
62 lines
1.2 KiB
Verilog
module dv_ctrl(/*AUTOARG*/
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// Outputs
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nreset, clk, start,
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// Inputs
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dut_active, stim_done, test_done
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);
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parameter CLK_PERIOD = 10;
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parameter CLK_PHASE = CLK_PERIOD/2;
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parameter TIMEOUT = 100000;
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output nreset; // async active low reset
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output clk; // main clock
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output start; // start test (level)
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input dut_active; // reset sequence is done
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input stim_done; //stimulus is done
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input test_done; //test is done
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//signal declarations
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reg nreset = 1'b0;
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reg clk = 1'b0;
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reg start;
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//init
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initial
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begin
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#(CLK_PERIOD*20) //hold reset for 20 cycles
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nreset = 'b1;
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end
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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start = 1'b0;
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else if(dut_active)
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start = 1'b1;
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always @ (posedge clk)
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if(stim_done & test_done)
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#(TIMEOUT) $finish;
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//Clock generator
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always
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#(CLK_PHASE) clk = ~clk;
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//Waveform dump
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//Better solution?
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`ifdef NOVCD
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`else
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initial
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begin
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$dumpfile("waveform.vcd");
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$dumpvars(0, dv_top);
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end
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`endif
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endmodule // dv_ctrl
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