oh/chip/docs/glossary.md

Chip Design Glossary

Chip Architecture

• ADC: Analog to Digital Converter
• Adder: Circuit to add two numbers
• Arbiter: Arbitrates between competing requesters
• ASIC: Application specific integrated circuit.
• CPU: Central processing unit
• CSA: Carry save adder
• DAC: Digital to Analog Converter
• DDS: Direct digital synthesis
• DSP: Digital signal processor
• Ethernet: Family of standard network technologies
• FPGA: Field-programmable gate array is a chip that can be reprogrammed "in the field".
• FIFO: First in first out buffer
• DRAM: Dynamic random-access semiconductor memory
• Flash: Non-volatile semiconductor memory
• FPU: Floating point unit
• GPIO: IO controllale at run time
• Gray code: Binary system where successive values differ by one bit
• I2C: Multi-master 2 wire bus
• LVDS: Low-voltage differential signaling (also TIA/EIA-644)
• MUX: Multiplexer
• Multiplier: Binary multiplier
• NCO: Numerically controlled oscillator
• NOC: Network on a chip
• PCIe: High Speed serial computer expansion bus
• PIC: Programmable interrupt controller
• PLL: Phase locked loop
• PWM: Pulse width modulation
• Q: Q fixed point number format
• ROM: Read only memory (denser than RAM)
• Schmitt Trigger: Comparitor circuit wityh
• SPI: Synchronous 4 wirem aster/slave interface
• SRAM: Static random access semiconductor memory
• UART: Asynchronous 2 wire point to point interface
• USB: 2 wire point to point 5 V interface
• 8b10b: Code that maps 8-bits to 10bit DC balanced symbols

Chip Design

• Antenna effect: Plasma induced gate oxide damage that can occur during semiconductor processing.
• BIST: Built in Self Test
• Chip: A set of electronic circuits on one small plate ("chip") of semiconductor material, normally silicon.
• Clock gating: Technique whereby clock in synchronous logic is shut off when idle.
• CMOS: Complimentary metal-oxide semiconductor
• Cross talk: The coupling of nearby signals on a chip, usually through capacitive coupling.
• DEF: Design Exchange Format for layout
• DFM: Extended DRC rules specifying how to make a high yielding design.
• DFT: Design for test
• Die: Small block of semiconductor material that can be cut ("diced") from a silicon wafer.
• DRC: Design Rule Constraints specifying manufacturing constraints.
• DV: Design verification is the process of verifying that the logic design conforms to specification.
• EDA: Electronic Design Automation tools used to enhance chip design productivity.
• Electromigration: Transport of material caused by the gradual movement of the ions in a conductor.
• EMI: Electromagnetic interference.
• ESD: Electrostatic discharge is the sudden flow of electricity between two electrically charged objects.
• Fabless: The design and sale of semiconductor devices while outsourcing the manufacturing to 3rd party.
• FEOL: Front end of line processing. Includes all chop processing up to but not including metal interconnect layers.
• Flip-flop: A clocked circuit that has two stable states and can be used to store state information.
• Foundry: Semiconductor company offering manufacturing services.
• GDSII: Binary format of design database sent to foundry.
• HDL: Specialized hardware description lanaguage for describing electronic circuits.
• IP: Semiconductor reusable design blocks containing author's Intellectual Property.
• IP Vendors: List of commercial semiconductor IP vendors.
• Jitter: Deviation from perfect periodicity.
• Latchup: Short circuit due to inadvertent creation of a low-impedance path between the power supply rails of a MOSFET circuit.
• Layout: Physical representation of an integrated circuit.
• LEF: Standard Cell Library Exchange Format layout.
• Logical Effort: Technique used to normalize (and optimize) digital circuits speed paths.
• LVS: Layout Versus Schematic software checks that the layout is identical to the netlist.
• Mask Works: Copyright law dedicated to 2D and 3D integrated circuit "layouts".
• MLS: Packaging and handling precautions for some semiconductors.
• Moore's Law: Observation by Gordon Moore that the number of transistors in an IC doubles approximately every two years.
• MOSIS: Foundry service project offering MPWs and low volume manufacturing.
• MPW: Multi-project wafer service that integrates multiple designs on one reticle (aka "shuttle").
• Multi-threshold CMOS: CMOS technology with multiple transistor types with different threshold voltages.
• Optical proximity correction: Technique used to compensate for semiconductor diffraction/process effects.
• PDK: Process design kits consist of a set of minimum set of files needed to design in a specific process.
• Power gating: Technique used to reduce leakage/standby power by shutting of the supply to the circuit.
• P&R: Automated Place and Route of a circuit using an EDA tool
• PVT Corners: Represents the extreme process, voltage, temperature that could occur in a given semiconductor process.
• RTL: Design abstraction for digital circuit design
• SEU: Change of state caused by one single ionizing particle (ions, electrons, photons...).
• Signoff: The final approval that the design is ready to be sent to foundry for manufacturing.
• SOC: System On Chip
• Spice: Open source analog electronic circuit simulator
• STA: Method of computing the expected timing of a digital circuit without requiring full circuit simulation.
• Standard Cell Design: Design process relying on a fixed set of standard cells.
• Synthesis: Translation of high level design description (eg Verilog) to a netlist format (eg standard cell gate level)
• SystemC: Set of C+ class and macros for simulation. Commonly used for high level modeling and testing
• Tape-out: Act of sending photomask chip database ("layout") to the manufacturer.
• TCL: Scripting language used by most of the leading EDA chip design tools.
• Verilog: Hardware description language (HDL)
• VLSI: Very large Integrated Circuit (somewhat outdated term, everything is VLSI today)

Manufacturing

• BEOL: Back end of line processing for connecting together devices using metal interconnects.
• Dicing: Act of cutting up wafer into individual dies
• FinFet: Non planar, double-gate transistor.
• Photo-lithography: Process used in micro-fabrication to pattern parts of a thin film or the bulk of a substrate.
• Photomasks: Opaque plates with holes or transparencies that allow light to shine through in a defined pattern.
• Reticle: A set of photomasks used by a stepper to step and print patterns onto a silicon wafer.
• Semiconductor Fabrication: Process used to create the integrated circuits
• Silicon: Element (Si) forms the basis of the electronic revolution.
• Silicon on insulator: Layered silicon–insulator–silicon substrate in place to reduce parasitic device capacitance.
• Stepper: Machine that passes light through reticle onto the silicon wafer being processed.
• TSV: Vertical electrical connection (via) passing completely through a silicon wafer or die.
• Wafer: Thin slice of semiconductor material used in electronics for the fabrication of integrated circuits.
• Wafer thinning: Wafer thickness is reduced to allow for stacking and high density packaging.

Packaging

• 3D IC's: The process of stacking integrated circuits and connecting them through TSVs.
• BGA: Ball grid array is a type of surface-mount packaging (a chip carrier) used for integrated circuits.
• BGA substrate: A miniaturized PCB that mates the silicon die to BGA pins.
• Bumping: Placing of bumps on wafer/dies in preparation for package assembly
• Flip-chip: Method of bonding a silicon die to package using solder bumps
• IC Assembly: Semiconductor die is encased in a supporting case "package".
• Interposer: Electrical interface used to spread a connection to a wider pitch.
• KGD: Known Good Die. Dies that have been completely tested at wafer probe.
• Leadframe: Metal structure inside a chip package that carry signals from the die to the outside.
• POP: Package on Package
• SIP: System In Package
• SMT: Technique whereby packaged chips are mounted directly onto the PCB surface.
• Wirebond: Method of bonding a silicon die to a package using wires
• WSI: Wafer scale integration

Test

• Arbitrary Waveform Generator: Electronic instrument used to generate arbitrary signal waveforms.
• ATE: Automatic Test Equipment for testing integrated circuits
• Burn-in: Process of screening parts for potential premature life time failures.
• DIB: Device Interface Board for interfacng DUT to ATE. Also called DUT board, probe card, load board, PIB.
• DMM: Electronic instrument for measuring voltage, current, and resistance.
• DUT: Device under test
• JTAG: Industry standard for verifying and testing/debugging printed circuit boards after manufacturing.
• Logic Analyzer: Electronic instrument for capturing multiple digital signal from a system.
• MCM: Multi-chip Module
• Oscilloscope: Electronic instrument for tracking the change of an electrical signal over time.
• Probe Card: A direct interface between electronic test systems and a semiconductor wafer
• Spectrum Analyzer: Electronic instrument for measuring the power of the spectrum of an unknown signal.