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108 lines
3.4 KiB
Verilog
108 lines
3.4 KiB
Verilog
// ###############################################################
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// # FUNCTION: Synchronous clock divider that divides by integer
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// # divcfg: 0 = div1
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// # 1 = div2
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// # 2 = div4
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// # 3 = div8
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// # 4 = div16
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// # 5 = div32
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// # 6 = div64
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// # 7 = div128
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// # 15:8= reserved
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// ###############################################################
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module oh_clockdiv(/*AUTOARG*/
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// Outputs
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clkout, clkout90,
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// Inputs
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clk, en, nreset, divcfg
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);
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//signals
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input clk; // input clock
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input en; // synchronous clock enable
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input nreset; // async
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input [3:0] divcfg; // divide factor (1-128)
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output clkout; // divided clock phase aligned with clkin
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output clkout90; // clkout shifted by 90 deg
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//regs
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reg clkout_reg;
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reg clkout90_reg;
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reg [7:0] counter;
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reg [7:0] divcfg_dec;
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reg [3:0] divcfg_reg;
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reg clkout90_div2;
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wire posedge_match;
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wire negedge_match;
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// divider setting
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always @ (divcfg_reg[3:0])
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casez (divcfg_reg[3:0])
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4'b0001 : divcfg_dec[7:0] = 8'b00000010; // Divide by 2
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4'b0010 : divcfg_dec[7:0] = 8'b00000100; // Divide by 4
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4'b0011 : divcfg_dec[7:0] = 8'b00001000; // Divide by 8
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4'b0100 : divcfg_dec[7:0] = 8'b00010000; // Divide by 16
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4'b0101 : divcfg_dec[7:0] = 8'b00100000; // Divide by 32
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4'b0110 : divcfg_dec[7:0] = 8'b01000000; // Divide by 64
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4'b0111 : divcfg_dec[7:0] = 8'b10000000; // Divide by 128
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default : divcfg_dec[7:0] = 8'b00000000; // others (divide by 1)
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endcase
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// divcfg change detector
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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divcfg_reg[3:0]<='b0; //set to bypass when in reset (fast clocks)
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else
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divcfg_reg[3:0]<=divcfg[3:0];
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assign cfg_reset = (|(divcfg_reg[3:0] ^ divcfg[3:0]));
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// synchronous edge counter
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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counter[7:0] <= 8'b00000001;
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else if(posedge_match | cfg_reset)
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counter[7:0] <= 8'b00000001;// Self resetting
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else if (en)
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counter[7:0] <= (counter[7:0] + 8'b00000001);
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assign posedge_match = (counter[7:0]==divcfg_dec[7:0]);
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assign negedge_match = (counter[7:0]=={1'b0,divcfg_dec[7:1]});
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assign posedge90_match = (counter[7:0]=={2'b0,divcfg_dec[7:2]});
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assign negedge90_match = (counter[7:0]=={2'b0,divcfg_dec[7:2]}+{1'b0,divcfg_dec[7:1]});
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// clkout
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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clkout_reg <= 1'b0;
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else if(posedge_match)
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clkout_reg <= 1'b1;
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else if(negedge_match)
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clkout_reg <= 1'b0;
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// divide by one special case
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assign clkout = (divcfg_reg[3:0]==4'b0000) ? clk : clkout_reg;
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// clkout90
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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clkout90_reg <= 1'b0;
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else if(posedge90_match)
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clkout90_reg <= 1'b1;
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else if(negedge90_match)
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clkout90_reg <= 1'b0;
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// special div2 case, using negedge of clk to delay by 90 deg
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always @ (negedge clk)
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clkout90_div2 <= clkout_reg;
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// divide by one and two special cases
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assign clkout90 = (divcfg_reg[3:0]==4'b0000) ? clk :
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(divcfg_reg[3:0]==4'b0001) ? clkout90_div2 :
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clkout90_reg;
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endmodule // oh_clockdiv
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