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49 lines
1.2 KiB
Verilog
49 lines
1.2 KiB
Verilog
//##################################################################
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//# ***DUAL DATA RATE OUTPUT***
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//#
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//# * Equivalent to "SAME_EDGE" for xilinx
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//# * din1/din2 presented together on rising edge of clk
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//# * din1 follows rising edge
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//# * din2 follows falling edge
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//##################################################################
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module oh_oddr (/*AUTOARG*/
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// Outputs
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out,
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// Inputs
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clk, ce, din1, din2
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);
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//parameters
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parameter DW = 32;
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//signals
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input clk; // clock input
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input ce; // clock enable input
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input [DW-1:0] din1; // data input1
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input [DW-1:0] din2; // data input2
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output [DW-1:0] out; // ddr output
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//regs("sl"=stable low, "sh"=stable high)
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reg [DW-1:0] q1_sl;
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reg [DW-1:0] q2_sl;
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reg [DW-1:0] q2_sh;
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//Generate different logic based on parameters
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always @ (posedge clk)
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if (ce)
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begin
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q1_sl[DW-1:0] <= din1[DW-1:0];
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q2_sl[DW-1:0] <= din2[DW-1:0];
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end
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always @ (negedge clk)
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q2_sh[DW-1:0] <= q2_sl[DW-1:0];
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assign out[DW-1:0] = clk ? q1_sl[DW-1:0] :
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q2_sh[DW-1:0];
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endmodule // oh_oddr
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