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109 lines
3.3 KiB
Verilog
109 lines
3.3 KiB
Verilog
//# REFERENCE:
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//# [0] https://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus
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//# [1] http://www.nxp.com/files/microcontrollers/doc/ref_manual/M68HC11RM.pdf
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//# [2] http://www.atmel.com/images/doc32017.pdf
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//# [3] https://www.adafruit.com/datasheets/1897_datasheet.pdf
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//# [4] https://www.analog.com/media/en/technical-documentation/application-notes/56755538964965031881813AN_877.pdf?doc=AD9652.pdf
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module spi (/*AUTOARG*/
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// Outputs
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reg_rdata, spi_irq, m_sclk, m_mosi, m_ss, s_miso,
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// Inputs
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nreset, clk, reg_access, reg_packet, m_miso, s_sclk, s_mosi, s_ss
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);
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//##################################################################
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//# INTERFACE
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//##################################################################
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parameter AW = 32; // data width of fifo
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parameter PW = 2*AW+40; // packet size
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parameter DEPTH = 32; // fifo depth
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//clk+reset
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input nreset; // asynchronous active low reset
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input clk; // write clock
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//register access
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input reg_access; // register access (read only)
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input [PW-1:0] reg_packet; // data/address
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output [31:0] reg_rdata; // readback data
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//interrupt
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output spi_irq; // interrupt output
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//master spi
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output m_sclk; // master clock
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output m_mosi; // master output
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output m_ss; // slave select
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input m_miso; // master input
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//slave spi
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input s_sclk; // slave clock
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input s_mosi; // slave input
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input s_ss; // slave select
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output s_miso; // slave output
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//##################################################################
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//# BODY
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//##################################################################
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire access; // From spi_rx of spi_rx.v
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wire cpha; // From spi_regs of spi_regs.v
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wire cpol; // From spi_regs of spi_regs.v
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wire miso; // From spi_tx of spi_tx.v
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wire mosi; // From spi_tx of spi_tx.v
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wire [7:0] rxdata; // From spi_rx of spi_rx.v
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wire sclk; // From spi_tx of spi_tx.v
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wire ss; // From spi_tx of spi_tx.v
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wire [7:0] txdata; // From spi_regs of spi_regs.v
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// End of automatics
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spi_regs spi_regs (/*AUTOINST*/
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// Outputs
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.reg_rdata (reg_rdata[31:0]),
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.cpol (cpol),
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.cpha (cpha),
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.txdata (txdata[7:0]),
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// Inputs
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.nreset (nreset),
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.clk (clk),
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.reg_access (reg_access),
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.reg_packet (reg_packet[PW-1:0]),
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.rxdata (rxdata[7:0]));
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spi_tx spi_tx (/*AUTOINST*/
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// Outputs
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.sclk (sclk),
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.mosi (mosi),
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.miso (miso),
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.ss (ss),
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// Inputs
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.nreset (nreset),
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.clk (clk),
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.access (access),
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.txdata (txdata[7:0]),
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.cpol (cpol),
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.cpha (cpha));
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spi_rx spi_rx (/*AUTOINST*/
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// Outputs
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.access (access),
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.rxdata (rxdata[7:0]),
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// Inputs
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.nreset (nreset),
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.clk (clk),
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.cpol (cpol),
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.cpha (cpha),
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.sclk (sclk),
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.mosi (mosi),
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.miso (miso),
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.ss (ss));
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endmodule // spi
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