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140 lines
4.1 KiB
Verilog
140 lines
4.1 KiB
Verilog
/*
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########################################################################
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RESET AND CLOCK CONFIG
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########################################################################
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*/
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module ecfg_clocks (/*AUTOARG*/
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// Outputs
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soft_reset, ecfg_clk_settings,
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// Inputs
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txwr_access, txwr_packet, txwr_access_out, clk, hard_reset
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);
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parameter RFAW = 6; // 32 registers for now
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parameter PW = 104; // 32 registers for now
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parameter ID = 12'h000;
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/******************************/
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/*REGISTER ACCESS */
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/******************************/
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input txwr_access;
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input [PW-1:0] txwr_packet;
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/******************************/
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/*FILTERED WRITE FOR TX FIFO */
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/******************************/
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output txwr_access_out;
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/******************************/
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/*Clock/reset */
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/******************************/
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input clk;
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input hard_reset; // ecfg registers reset only by "hard reset"
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/******************************/
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/*Outputs */
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/******************************/
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output soft_reset; // soft reset output driven by register
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output [15:0] ecfg_clk_settings; // clock settings (for pll)
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/*------------------------CODE BODY---------------------------------------*/
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//registers
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reg ecfg_reset_reg;
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reg [15:0] ecfg_clk_reg;
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reg [11:0] ecfg_coreid_reg;
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reg [15:0] ecfg_version_reg;
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reg [31:0] mi_dout;
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//wires
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wire ecfg_read;
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wire ecfg_write;
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wire ecfg_clk_write;
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wire ecfg_coreid_write;
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wire ecfg_version_write;
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wire ecfg_reset_write;
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wire mi_en;
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wire [31:0] mi_addr;
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wire [31:0] mi_din;
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packet2emesh pe2 (
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// Outputs
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.access_out (),
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.write_out (mi_we),
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.datamode_out (),
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.ctrlmode_out (),
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.dstaddr_out (mi_addr[31:0]),
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.data_out (mi_din[31:0]),
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.srcaddr_out (),
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// Inputs
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.packet_in (txwr_packet[PW-1:0])
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);
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/*****************************/
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/*ADDRESS DECODE LOGIC */
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/*****************************/
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assign mi_en = txwr_access &
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(mi_addr[31:20]==ID) &
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(mi_addr[10:8]==3'h2);
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//read/write decode
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assign ecfg_write = mi_en & mi_we;
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assign ecfg_read = mi_en & ~mi_we;
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//Config write enables
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assign ecfg_reset_write = ecfg_write & (mi_addr[RFAW+1:2]==`E_RESET);
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assign ecfg_clk_write = ecfg_write & (mi_addr[RFAW+1:2]==`E_CLK);
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/*****************************/
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/*FILTER ACCESS */
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/*****************************/
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assign txwr_access_out = txwr_access & ~(ecfg_reset_write | ecfg_clk_write );
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//###########################
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//# RESET
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//###########################
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always @ (posedge clk or posedge hard_reset)
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if(hard_reset)
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ecfg_reset_reg <= 1'b0;
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else if (ecfg_reset_write)
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ecfg_reset_reg <= mi_din[0];
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assign soft_reset = ecfg_reset_reg;
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//###########################
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//# CCLK/LCLK (PLL)
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//###########################
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always @ (posedge clk or posedge hard_reset)
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if(hard_reset)
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ecfg_clk_reg[15:0] <= 16'h573;//all clocks on at lowest speed
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else if (ecfg_clk_write)
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ecfg_clk_reg[15:0] <= mi_din[15:0];
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assign ecfg_clk_settings[15:0] = ecfg_clk_reg[15:0];
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endmodule // ecfg_base
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// Local Variables:
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// verilog-library-directories:("." "../../common/hdl")
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// End:
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/*
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Copyright (C) 2013 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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