mirror of
https://github.com/aolofsson/oh.git
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20534a6ed1
-pin driven testmode driven..b/c fpga designers often don't like software -and because it's really convenient, press a push button and see a pattern appear -removed protocol description, goes in README.md, there should only be one source for documentation -shortened signal names for ecfg -changed to "clk" input now that everything is single clock
204 lines
6.1 KiB
Verilog
204 lines
6.1 KiB
Verilog
module etx_protocol (/*AUTOARG*/
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// Outputs
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etx_rd_wait, etx_wr_wait, etx_wait, etx_io_wait, tx_frame_par,
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tx_data_par,
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// Inputs
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reset, clk, testmode, etx_access, etx_packet, tx_enable, tp_enable,
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gpio_enable, gpio_data, chipid, tx_rd_wait, tx_wr_wait
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);
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parameter PW = 104;
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parameter AW = 32;
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parameter DW = 32;
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parameter ID = 12'h000;
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//Clock/reset
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input reset;
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input clk;
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//Puts transmit in testmode
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input testmode;
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//System side
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input etx_access;
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input [PW-1:0] etx_packet;
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//Pushback signals
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output etx_rd_wait;
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output etx_wr_wait;
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output etx_wait; //for pipeline
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output etx_io_wait; //for arbiter
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//Enble transmit
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input tx_enable; //transmit enable
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input tp_enable; //testmode enable
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input gpio_enable;//gpio enable
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input [8:0] gpio_data; //gpio mode data
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input [11:0] chipid; //chip id
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//Interface to IO
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output [7:0] tx_frame_par;
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output [63:0] tx_data_par;
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input tx_rd_wait; // The wait signals are passed through
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input tx_wr_wait; // to the emesh interfaces
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//###################################################################
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//# Local regs & wires
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//###################################################################
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reg etx_sample; //hold for second cycle
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reg [7:0] tx_frame_par;
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reg [127:0] tx_data_reg; //sample transaction on one clock cycle
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reg rd_wait_sync;
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reg wr_wait_sync;
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wire etx_write;
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wire [1:0] etx_datamode;
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wire [3:0] etx_ctrlmode;
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wire [AW-1:0] etx_dstaddr;
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wire [DW-1:0] etx_data;
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wire [AW-1:0] etx_srcaddr;
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wire [PW-1:0] etx_packet_mux;
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reg [PW-1:0] testpacket;
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//Testmode logic
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always @( posedge clk or posedge reset )
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if(reset)
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testpacket[PW-1:0] <= 'd0;
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else if(testmode)
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if(~testpacket[1])//initiate write
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testpacket[PW-1:0]<={32'h55555555,//src
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32'h55555555,//data
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chipid[11:0],20'b0,//dst
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4'b0,2'b10,2'b11};//32bit write
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else //initiate read
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testpacket[PW-1:0]<={ID,12'hF03,`ERX_RR,2'b0,//src
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32'haaaaaaaa,//dummy data
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chipid[11:0],20'b0,//read from address
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4'b0,2'b10,2'b01};//32bit read
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assign etx_packet_mux[PW-1:0] = testmode ? testpacket[PW-1:0] :
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etx_packet[PW-1:0];
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//Access always on in test mode (assumes no other traffic)
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assign etx_access_mux = testmode | etx_access;
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//Transmit packet enable
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assign etx_enable = testmode | tx_enable;
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//packet to emesh bundle
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packet2emesh p2m (
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// Outputs
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.access_out (),
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.write_out (etx_write),
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.datamode_out (etx_datamode[1:0]),
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.ctrlmode_out (etx_ctrlmode[3:0]),
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.dstaddr_out (etx_dstaddr[31:0]),
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.data_out (etx_data[31:0]),
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.srcaddr_out (etx_srcaddr[31:0]),
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// Inputs
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.packet_in (etx_packet_mux[PW-1:0])
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);
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// TODO: Bursts
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always @( posedge clk or posedge reset )
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begin
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if(reset)
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begin
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etx_sample <= 1'b1;
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tx_frame_par[7:0] <= 8'd0;
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tx_data_reg[127:0] <= 'd0;
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end
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else
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begin
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if( etx_enable & etx_access & etx_sample ) //first cycle
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begin
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etx_sample <= 1'b0;
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tx_frame_par[7:0] <= 8'h3F;
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tx_data_reg[127:0] <= {etx_data[31:0],
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etx_srcaddr[31:0],
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8'd0, // Not used
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8'd0, //not used
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~etx_write, 7'd0, // B0-TODO: For bursts, add the inc bit
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etx_ctrlmode[3:0], etx_dstaddr[31:28], // B1
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etx_dstaddr[27:4], // B2, B3, B4
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etx_dstaddr[3:0], etx_datamode[1:0], etx_write, etx_access // B5
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};
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end
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else if(etx_enable & ~etx_sample ) //second cycle (1)
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begin
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etx_sample <= 1'b1;
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tx_frame_par[7:0] <= 8'hFF;
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end
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else
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begin
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etx_sample <= 1'b1;
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tx_frame_par[7:0] <= 'd0;
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tx_data_reg[127:0] <= 'd0;
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end
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end // else: !if(reset)
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end // always @ ( posedge txlclk_p or posedge reset )
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//After first sample, etx_sample-->0 use as indicator to sample in data.
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assign tx_data_par[63:0] = ~etx_sample ? tx_data_reg[63:0] : //first cycle
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tx_data_reg[127:64];//all others, 0 or upper
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//#############################
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//# Wait signals (async)
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//#############################
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synchronizer #(.DW(1)) rd_sync (// Outputs
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.out (etx_rd_wait),
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// Inputs
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.in (tx_rd_wait),
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.clk (clk),
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.reset (reset)
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);
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synchronizer #(.DW(1)) wr_sync (// Outputs
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.out (etx_wr_wait),
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// Inputs
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.in (tx_wr_wait),
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.clk (clk),
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.reset (reset)
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);
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//#############################
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//# Pipeline stall
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//#############################
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assign etx_io_wait = ~etx_sample;
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assign etx_wait = etx_io_wait |
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etx_rd_wait |
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etx_wr_wait;
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endmodule // etx_protocol
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// Local Variables:
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// verilog-library-directories:("." "../../common/hdl")
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// End:
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/*
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File: etx_protocol.v
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This file is part of the Parallella Project.
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Fred Huettig <fred@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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