Andreas Olofsson 69f3df4140 Continued work to create clean design: ...

-pll bypass for clocks (customer request)
-adding dividers on all clocks (tx/cclk)
-adding reset block (clearer)
-using commong clock_divider block
-need to clean up divider block later today, slightly broken:-)

2015-04-15 11:54:43 -04:00

..

dv_ecfg.v

Cleanup

2015-04-11 00:12:57 -04:00

dv_elink_tb.v

Adding different data modes

2015-04-14 23:47:49 -04:00

dv_elink.v

Continued work to create clean design:

2015-04-15 11:54:43 -04:00

elink.cmd

Running with "TARGET_CLEAN"

2015-04-14 23:48:58 -04:00

run.sh

Verilator lint cleanup

2015-04-14 14:00:23 -04:00