Andreas Olofsson 69f3df4140 Continued work to create clean design: ...

-pll bypass for clocks (customer request)
-adding dividers on all clocks (tx/cclk)
-adding reset block (clearer)
-using commong clock_divider block
-need to clean up divider block later today, slightly broken:-)

2015-04-15 11:54:43 -04:00

..

fifo_async_emesh.v

Adding platform agnostic dual ported memory and async fifo

2015-04-14 23:56:00 -04:00

fifo_async.v

Adding platform agnostic dual ported memory and async fifo

2015-04-14 23:56:00 -04:00

fifo_empty_block.v

Support files for fifo

2015-04-14 23:56:59 -04:00

fifo_full_block.v

Support files for fifo

2015-04-14 23:56:59 -04:00

fifo_mem.v

Continued work to create clean design:

2015-04-15 11:54:43 -04:00

fifo_sync.v

Verilator lint cleanup

2015-04-14 14:00:23 -04:00

memory_dp.v

Adding platform agnostic dual ported memory and async fifo

2015-04-14 23:56:00 -04:00

memory_sp.v

Reorganizing structure to be IP centric

2014-11-05 14:31:05 -05:00