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86 lines
2.2 KiB
Verilog
86 lines
2.2 KiB
Verilog
module pi2c (/*AUTOARG*/
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// Outputs
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i2c_sda_i, i2c_scl_i,
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// Inouts
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i2c_sda, i2c_scl,
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// Inputs
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i2c_sda_o, i2c_sda_t, i2c_scl_o, i2c_scl_t
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);
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parameter PORTABLE = 0;
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input i2c_sda_o;
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input i2c_sda_t;
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output i2c_sda_i;
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input i2c_scl_o;
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input i2c_scl_t;
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output i2c_scl_i;
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inout i2c_sda;
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inout i2c_scl;
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generate
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if(PORTABLE==1) begin
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wire i2c_sda = i2c_sda_t ? 1'bz: i2c_sda_o;
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wire i2c_sda_i = i2c_sda;
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wire i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
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wire i2c_scl_i = i2c_scl;
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end
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else
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begin
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IOBUF #(
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.DRIVE(8), // Specify the output drive strength
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.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
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.IOSTANDARD("DEFAULT"), // Specify the I/O standard
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.SLEW("SLOW") // Specify the output slew rate
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) i_sda (
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.O(i2c_sda_i), // Buffer output
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.IO(i2c_sda), // Buffer inout port (connect directly to top-level port)
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.I(i2c_sda_o), // Buffer input
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.T(i2c_sda_t) // 3-state enable input, high=input, low=output
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);
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IOBUF #(
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.DRIVE(8),
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.IBUF_LOW_PWR("TRUE"),
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.IOSTANDARD("DEFAULT"),
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.SLEW("SLOW")
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) i_scl (
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.O(i2c_scl_i),
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.IO(i2c_scl),
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.I(i2c_scl_o),
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.T(i2c_scl_t)
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);
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end
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endgenerate
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endmodule // pi2c
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/*
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File: parallella_i2c
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This file is part of the Parallella FPGA Reference Design.
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Copyright (C) 2013-2015 Adapteva, Inc.
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Contributed by Fred Huettig
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Contributed by Andreas Olofsson
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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